Lines Matching refs:x8
363 #define KPAD_PRESSED 0x8 /* Key press current status */
374 #define XFER_DIR 0x8 /* Transfer Direction */
400 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
412 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
424 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
502 #define RESET 0x8 /* Reset indicator */
513 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
523 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
534 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
544 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
555 #define SOF_B 0x8 /* Start of frame */
566 #define SOF_BE 0x8 /* Start of frame int enable */
585 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
603 #define VBUS0 0x8 /* Vbus level indicator[0] */
614 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
623 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
632 #define DATAEND 0x8 /* Data end indicator */
639 #define SETUPPKT_H 0x8 /* send Setup token host mode */
666 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
689 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
734 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
745 #define INT_ENA 0x8 /* Interrupt enable */