Lines Matching refs:BFIN_IRQ
41 #define BFIN_IRQ(x) ((x) + 7)
43 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44 #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
45 #define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
46 #define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
47 #define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
48 #define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
49 #define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
50 #define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
51 #define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
52 #define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
53 #define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
54 #define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
55 #define IRQ_RTC BFIN_IRQ(14) /* RTC */
56 #define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
57 #define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
58 #define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
59 #define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
60 #define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
61 #define IRQ_TWI BFIN_IRQ(20) /* TWI */
62 #define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
63 #define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
64 #define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
65 #define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
66 #define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
67 #define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
68 #define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
69 #define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
70 #define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
71 #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
72 #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
73 #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
74 #define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
75 #define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
76 #define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
77 #define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
78 #define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
79 #define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
80 #define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
81 #define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
82 #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
83 #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
84 #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
85 #define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
86 #define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
87 #define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
88 #define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
89 #define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
90 #define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
91 #define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
92 #define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
93 #define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
94 #define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
95 #define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
96 #define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
97 #define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
99 #define SYS_IRQS BFIN_IRQ(63) /* 70 */