Lines Matching refs:ah
25 #include "ah.h"
107 static HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask);
149 ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,
155 struct ath_hal_5211 *ahp = AH5211(ah);
168 HALDEBUG(ah, HAL_DEBUG_RESET,
173 OS_MARK(ah, AH_MARK_RESET, bChannelChange);
176 HALDEBUG(ah, HAL_DEBUG_ANY,
182 HALDEBUG(ah, HAL_DEBUG_ANY,
191 ichan = ath_hal_checkchannel(ah, chan);
193 HALDEBUG(ah, HAL_DEBUG_ANY,
205 HALDEBUG(ah, HAL_DEBUG_ANY,
210 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);
229 saveTsfLow = OS_REG_READ(ah, AR_TSF_L32);
230 saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32);
233 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
234 saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM);
237 saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i));
248 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
253 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
256 ledstate = OS_REG_READ(ah, AR_PCICFG) &
259 softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
260 softLedState = OS_REG_READ(ah, AR_GPIODO);
262 if (!ar5211ChipReset(ah, chan->channelFlags)) {
263 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
292 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
293 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
295 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
299 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
301 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) {
302 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
323 OS_REG_WRITE(ah, ar5211Mode2_4[i][0],
328 ar5211SetRf6and7(ah, chan);
332 OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]);
336 OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]);
343 OS_REG_WRITE(ah, reg, ar5211Common[i][1]);
347 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
354 data = OS_REG_READ(ah, AR_USEC);
357 OS_REG_WRITE(ah, AR_USEC,
361 OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0);
364 OS_REG_WRITE(ah, 0x00009878, 0x00000008);
367 OS_REG_WRITE(ah, AR_DIAG_SW,
368 OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO);
374 OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow);
375 OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh);
377 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
378 OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]);
381 OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]);
385 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
386 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
389 ar5211SetOperatingMode(ah, opmode);
392 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
393 OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);
394 OS_REG_WRITE(ah, AR_GPIODO, softLedState);
397 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
399 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
400 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
403 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
405 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
412 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU &&
413 AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) {
414 OS_REG_WRITE(ah, AR_CFG,
415 OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS);
419 if (!ar5211SetTransmitPower(ah, chan)) {
420 HALDEBUG(ah, HAL_DEBUG_ANY,
430 (AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) {
432 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
434 MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1);
438 ar5211SetBoardValues(ah, chan);
440 if (!ar5211SetChannel(ah, ichan)) {
441 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
447 if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B && IS_CHAN_2GHZ(chan))
448 OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */
449 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
456 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M;
471 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
472 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
473 (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);
476 if (!ar5211CalNoiseFloor(ah, ichan)) {
479 HALDEBUG(ah, HAL_DEBUG_ANY,
486 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
493 OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q);
496 ar5211ResetTxQueue(ah, q);
499 OS_REG_WRITE(ah, AR_IMR_S0,
502 OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0));
503 OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0));
509 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS));
512 OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK);
516 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) |
521 OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB);
525 if (AH_PRIVATE(ah)->ah_rfkillEnabled)
526 ar5211EnableRfKill(ah);
534 OS_REG_WRITE(ah, AR_BEACON,
535 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
539 ar5211SetSifsTime(ah, ahp->ah_sifstime);
541 ar5211SetSlotTime(ah, ahp->ah_slottime);
543 ar5211SetAckTimeout(ah, ahp->ah_acktimeout);
545 ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout);
546 if (AH_PRIVATE(ah)->ah_diagreg != 0)
547 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
549 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
551 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
569 ar5211PhyDisable(struct ath_hal *ah)
571 return ar5211SetResetReg(ah, AR_RC_BB);
578 ar5211Disable(struct ath_hal *ah)
580 if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
586 if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
602 ar5211ChipReset(struct ath_hal *ah, uint16_t channelFlags)
604 if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
611 OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
612 OS_REG_WRITE(ah, AR5211_PHY_MODE,
614 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
620 OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
621 if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
622 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
624 OS_REG_WRITE(ah, AR5211_PHY_MODE,
631 OS_REG_WRITE(ah, AR_PHY_TURBO,
634 OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
636 if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
637 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
639 OS_REG_WRITE(ah, AR5211_PHY_MODE,
650 if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
655 if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
659 return ar5211SetResetReg(ah, 0);
667 ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
670 struct ath_hal_5211 *ahp = AH5211(ah);
678 ichan = ath_hal_checkchannel(ah, chan);
680 HALDEBUG(ah, HAL_DEBUG_ANY,
687 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
692 powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);
693 powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);
694 iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);
713 HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n",
715 HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n",
717 HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n",
719 HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff = %d\n",
721 HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff = %d\n",
725 data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
729 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);
736 if (!ar5211IsNfGood(ah, ichan)) {
742 if (!ar5211CalNoiseFloor(ah, ichan)) {
749 if (!ar5211CalNoiseFloor(ah, ichan)) {
755 ar5211RequestRfgain(ah);
761 ar5211PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
763 return ar5211PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
767 ar5211ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
777 ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)
782 (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */
783 OS_REG_WRITE(ah, AR_RC, resetMask);
790 rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
799 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
801 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
813 ar5211SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
818 chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
842 OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
844 OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
846 AH_PRIVATE(ah)->ah_curchan = chan;
851 ar5211GetNoiseFloor(struct ath_hal *ah)
855 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
868 ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)
875 OS_REG_WRITE(ah, AR_PHY(25),
876 (OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) |
879 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
880 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
899 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
904 HALDEBUG(ah, HAL_DEBUG_NFCAL,
906 runTime, AH_PRIVATE(ah)->ah_curchan->channel);
907 HALDEBUG(ah, HAL_DEBUG_NFCAL,
909 OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
910 HALDEBUG(ah, HAL_DEBUG_NFCAL,
912 OS_REG_READ(ah, AR_PHY_ACTIVE));
916 return ar5211GetNoiseFloor(ah);
920 getNoiseFloorThresh(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int16_t *nft)
922 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
935 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
948 ar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
952 if (!getNoiseFloorThresh(ah, chan, &nfThresh))
955 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
956 HALDEBUG(ah, HAL_DEBUG_ANY,
959 nf = ar5211GetNoiseFloor(ah);
961 HALDEBUG(ah, HAL_DEBUG_ANY,
985 ar5211CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
989 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU &&
990 ath_hal_getnfcheckrequired(ah, (HAL_CHANNEL *) chan)) {
995 if (!getNoiseFloorThresh(ah, chan, &nfThresh))
1002 nf = ar5211RunNoiseFloor(ah, runtime[i], 0);
1004 HALDEBUG(ah, HAL_DEBUG_ANY,
1015 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1016 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) |
1027 ar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
1059 ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
1062 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1063 struct ath_hal_5211 *ahp = AH5211(ah);
1124 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1154 OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]);
1164 ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
1169 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1170 struct ath_hal_5211 *ahp = AH5211(ah);
1179 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1209 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",
1215 OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);
1216 OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);
1228 ar5211SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *chan)
1230 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1231 struct ath_hal_5211 *ahp = AH5211(ah);
1237 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1247 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1253 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
1254 OS_REG_WRITE(ah, AR_PHY(68),
1255 (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3);
1257 OS_REG_WRITE(ah, AR_PHY(68),
1258 (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) |
1261 ar5211SetAntennaSwitchInternal(ah,
1265 OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),
1268 OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),
1269 (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |
1271 OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),
1272 (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |
1274 OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),
1275 (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |
1278 OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),
1283 OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),
1284 (OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |
1286 OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),
1287 (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |
1298 if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) {
1299 if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
1308 OS_REG_WRITE(ah, 0x9924,
1309 (OS_REG_READ(ah, 0x9924) & 0xFFFFFF01)
1324 ar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
1327 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
1328 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit);
1337 ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
1339 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1370 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1375 ar5211SetPowerTable(ah, &eepromPcdacs, chan->channel);
1379 cfgCtl = ath_hal_getctl(ah, chan);
1385 ar5211SetRateTable(ah, rep, pi, nchan, chan);
1397 ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, uint16_t channel)
1504 OS_REG_WRITE(ah, addr, temp32);
1515 ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
1519 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1520 struct ath_hal_5211 *ahp = AH5211(ah);
1547 twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain);
1645 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1
1647 && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
1660 (tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2);
1672 HALDEBUG(ah, HAL_DEBUG_RESET,
1675 HALDEBUG(ah, HAL_DEBUG_RESET,
1678 HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n",
1679 tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2,
1682 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1)
1683 HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n",
1685 HALDEBUG(ah, HAL_DEBUG_RESET,
1693 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1698 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1705 ar5211SetTxPowerLimit(ah, pRatesPower[0]);
1707 AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0];
1929 ar5211InitializeGainValues(struct ath_hal *ah)
1931 struct ath_hal_5211 *ahp = AH5211(ah);
1943 ar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)
1945 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
1977 ar5211RequestRfgain(struct ath_hal *ah)
1979 struct ath_hal_5211 *ahp = AH5211(ah);
1982 OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,
1994 ar5211GetRfgain(struct ath_hal *ah)
1996 struct ath_hal_5211 *ahp = AH5211(ah);
2005 rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);
2013 if (!ar5211InvalidGainReadback(ah, gv) &&
2014 ar5211IsGainAdjustNeeded(ah, gv) &&
2015 ar5211AdjustGain(ah, gv) > 0) {
2020 ar5211SetRfgain(ah, gv);
2033 ar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)
2042 ar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)
2051 HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2055 HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2064 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
2070 HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2074 HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2084 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
2095 ar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv)
2097 HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
2108 ar5211SetOperatingMode(struct ath_hal *ah, int opmode)
2110 struct ath_hal_5211 *ahp = AH5211(ah);
2113 val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
2116 OS_REG_WRITE(ah, AR_STA_ID1, val
2122 OS_REG_WRITE(ah, AR_STA_ID1, val
2129 OS_REG_WRITE(ah, AR_STA_ID1, val
2137 ar5211SetPCUConfig(struct ath_hal *ah)
2139 ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);