Lines Matching defs:dividers
726 struct pp_atomctrl_clock_dividers_ai dividers;
734 /* get the engine clock dividers for this clock value */
735 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
737 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
738 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
739 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
740 sclk_setting->PllRange = dividers.ucSclkPllRange;
742 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
744 sclk_setting->SSc_En = dividers.ucSscEnable;
745 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
746 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
747 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
1140 "Error retrieving Engine Clock dividers from VBIOS.",
1201 struct pp_atomctrl_clock_dividers_vi dividers;
1233 table->VceLevel[count].Frequency, ÷rs);
1238 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1314 struct pp_atomctrl_clock_dividers_vi dividers;
1345 table->UvdLevel[count].VclkFrequency, ÷rs);
1349 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1352 table->UvdLevel[count].DclkFrequency, ÷rs);
1356 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1932 pp_atomctrl_clock_dividers_vi dividers;
2107 smu_data->bif_sclk_table[i], ÷rs);
2114 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2117 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));