powerplay/smumgr/amdgpu_ci_smumgr.c

304 	struct pp_atomctrl_clock_dividers_vi dividers;
315 	/* get the engine clock dividers for this clock value */
316 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
319 			"Error retrieving Engine Clock dividers from VBIOS.",
324 	ref_divider = 1 + dividers.uc_pll_ref_div;
327 	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
331 			SPLL_REF_DIV, dividers.uc_pll_ref_div);
333 			SPLL_PDIV_A,  dividers.uc_pll_post_div);
346 		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
369 	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
1385 	struct pp_atomctrl_clock_dividers_vi dividers;
1406 	/* get the engine clock dividers for this clock value*/
1408 		table->ACPILevel.SclkFrequency,  &dividers);
1411 		"Error retrieving Engine Clock dividers from VBIOS.", return result);
1414 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1526 	struct pp_atomctrl_clock_dividers_vi dividers;
1542 				table->UvdLevel[count].VclkFrequency, &dividers);
1546 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1549 				table->UvdLevel[count].DclkFrequency, &dividers);
1553 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1567 	struct pp_atomctrl_clock_dividers_vi dividers;
1581 				table->VceLevel[count].Frequency, &dividers);
1586 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1599 	struct pp_atomctrl_clock_dividers_vi dividers;
1612 				table->AcpLevel[count].Frequency, &dividers);
1616 		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;