powerplay/hwmgr/amdgpu_ppatomctrl.c

249  * @param dividers                 output parameter: memory PLL dividers
301  * @param dividers               output parameter: memory PLL dividers
355 					  pp_atomctrl_clock_dividers_kong *dividers)
368 		dividers->pll_post_divider = pll_parameters.ucPostDiv;
369 		dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);
378 		pp_atomctrl_clock_dividers_vi *dividers)
392 		dividers->pll_post_divider =
394 		dividers->real_clock =
397 		dividers->ul_fb_div.ul_fb_div_frac =
399 		dividers->ul_fb_div.ul_fb_div =
402 		dividers->uc_pll_ref_div =
404 		dividers->uc_pll_post_div =
406 		dividers->uc_pll_cntl_flag =
415 		pp_atomctrl_clock_dividers_ai *dividers)
429 		dividers->usSclk_fcw_frac     = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
430 		dividers->usSclk_fcw_int      = le16_to_cpu(pll_patameters.usSclk_fcw_int);
431 		dividers->ucSclkPostDiv       = pll_patameters.ucSclkPostDiv;
432 		dividers->ucSclkVcoMode       = pll_patameters.ucSclkVcoMode;
433 		dividers->ucSclkPllRange      = pll_patameters.ucSclkPllRange;
434 		dividers->ucSscEnable         = pll_patameters.ucSscEnable;
435 		dividers->usSsc_fcw1_frac     = le16_to_cpu(pll_patameters.usSsc_fcw1_frac);
436 		dividers->usSsc_fcw1_int      = le16_to_cpu(pll_patameters.usSsc_fcw1_int);
437 		dividers->usPcc_fcw_int       = le16_to_cpu(pll_patameters.usPcc_fcw_int);
438 		dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac);
439 		dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac);
447 		pp_atomctrl_clock_dividers_vi *dividers)
462 		dividers->pll_post_divider =
464 		dividers->real_clock =
467 		dividers->ul_fb_div.ul_fb_div_frac =
469 		dividers->ul_fb_div.ul_fb_div =
472 		dividers->uc_pll_ref_div =
474 		dividers->uc_pll_post_div =
476 		dividers->uc_pll_cntl_flag =