amd/amdgpu/amdgpu_cz_ih.c

56 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
61  * @adev: amdgpu_device pointer
65 static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
74 	adev->irq.ih.enabled = true;
80  * @adev: amdgpu_device pointer
84 static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
96 	adev->irq.ih.enabled = false;
97 	adev->irq.ih.rptr = 0;
103  * @adev: amdgpu_device pointer
111 static int cz_ih_irq_init(struct amdgpu_device *adev)
113 	struct amdgpu_ih_ring *ih = &adev->irq.ih;
118 	cz_ih_disable_interrupts(adev);
121 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
132 	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
134 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
156 	if (adev->irq.msi_enabled)
160 	pci_set_master(adev->pdev);
163 	cz_ih_enable_interrupts(adev);
171  * @adev: amdgpu_device pointer
175 static void cz_ih_irq_disable(struct amdgpu_device *adev)
177 	cz_ih_disable_interrupts(adev);
186  * @adev: amdgpu_device pointer
194 static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
207 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
220  * @adev: amdgpu_device pointer
225 static void cz_ih_decode_iv(struct amdgpu_device *adev,
252  * @adev: amdgpu_device pointer
256 static void cz_ih_set_rptr(struct amdgpu_device *adev,
264 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
267 	ret = amdgpu_irq_add_domain(adev);
271 	cz_ih_set_interrupt_funcs(adev);
279 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
281 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
285 	r = amdgpu_irq_init(adev);
292 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
294 	amdgpu_irq_fini(adev);
295 	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
296 	amdgpu_irq_remove_domain(adev);
304 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
306 	r = cz_ih_irq_init(adev);
315 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
317 	cz_ih_irq_disable(adev);
324 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
326 	return cz_ih_hw_fini(adev);
331 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
333 	return cz_ih_hw_init(adev);
338 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
351 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353 	for (i = 0; i < adev->usec_timeout; i++) {
366 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
376 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
430 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
432 	adev->irq.ih_funcs = &cz_ih_funcs;