Lines Matching refs:rval
815 #define onoff2(str, rval, bit, onstr, offstr) \
817 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
818 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off")
834 pcireg_t rval;
837 rval = regs[o2i(PCI_CLASS_REG)];
838 class = PCI_CLASS(rval);
839 subclass = PCI_SUBCLASS(rval);
840 interface = PCI_INTERFACE(rval);
841 revision = PCI_REVISION(rval);
843 rval = regs[o2i(PCI_ID_REG)];
844 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval));
847 PCI_VENDOR(rval));
849 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
850 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval),
851 PCI_PRODUCT(rval));
854 PCI_PRODUCT(rval));
856 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
858 rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
860 printf(" Command register: 0x%04x\n", rval & 0xffff);
861 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
862 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
863 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
864 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
865 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
866 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
867 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
868 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
869 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
870 onoff("Fast back-to-back transactions", rval,
872 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
874 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
875 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS);
876 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
878 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
879 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
880 onoff("User Definable Features (UDF) support", rval,
882 onoff("Fast back-to-back capable", rval,
884 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
887 switch (rval & PCI_STATUS_DEVSEL_MASK) {
901 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK));
903 onoff("Slave signaled Target Abort", rval,
905 onoff("Master received Target Abort", rval,
907 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
908 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
909 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
911 rval = regs[o2i(PCI_CLASS_REG)];
954 subclassp->name, PCI_SUBCLASS(rval));
956 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
965 rval = regs[o2i(PCI_BHLC_REG)];
966 printf(" BIST: 0x%02x\n", PCI_BIST(rval));
967 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
968 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
969 PCI_HDRTYPE(rval));
970 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
971 num = PCI_CACHELINE(rval);
983 pcireg_t rval, rval64h;
989 rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
990 ioen = rval & PCI_COMMAND_IO_ENABLE;
991 memen = rval & PCI_COMMAND_MEM_ENABLE;
1005 rval = regs[o2i(reg)];
1006 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
1007 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
1014 if (rval != 0 && memen) {
1029 pci_conf_write(pc, tag, reg, rval);
1030 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
1031 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
1045 if (rval == 0) {
1050 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
1053 switch (PCI_MAPREG_MEM_TYPE(rval)) {
1067 if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
1072 switch (PCI_MAPREG_MEM_TYPE(rval)) {
1076 ((((long long) rval64h) << 32) | rval)));
1090 PCI_MAPREG_MEM_ADDR(rval));
1106 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval));
1185 pcireg_t rval;
1190 rval = regs[o2i(capoff)];
1192 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
1194 rval = regs[o2i(capoff + PCI_AGP_STATUS)];
1195 printf(" Status register: 0x%04x\n", rval);
1197 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1);
1199 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ));
1201 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL)));
1202 onoff("SBA", rval, AGP_MODE_SBA);
1203 onoff("htrans#", rval, AGP_MODE_HTRANS);
1204 onoff("Over 4G", rval, AGP_MODE_4G);
1205 onoff("Fast Write", rval, AGP_MODE_FW);
1206 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3);
1207 isagp3 = rval & AGP_MODE_MODE_3;
1209 pci_conf_print_agp_datarate(rval, isagp3);
1211 rval = regs[o2i(capoff + PCI_AGP_COMMAND)];
1212 printf(" Command register: 0x%08x\n", rval);
1214 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1);
1216 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ));
1218 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL)));
1219 onoff("SBA", rval, AGP_MODE_SBA);
1220 onoff("AGP", rval, AGP_MODE_AGP);
1221 onoff("Over 4G", rval, AGP_MODE_4G);
1222 onoff("Fast Write", rval, AGP_MODE_FW);
1230 pci_conf_print_agp_datarate(rval, isagp3);
2742 pcireg_t rval;
2763 off != 0; off = PCI_CAPLIST_NEXT(rval)) {
2764 rval = regs[o2i(off)];
2765 if (capid == PCI_CAPLIST_CAP(rval)) {
2783 pcireg_t rval;
2794 rval = regs[o2i(off)];
2797 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
2798 foundcap = PCI_CAPLIST_CAP(rval);
2823 rval = regs[o2i(off)];
2824 if ((PCI_CAPLIST_CAP(rval) == i)
4599 pcireg_t rval;
4603 off = PCI_EXTCAPLIST_NEXT(rval)) {
4604 rval = regs[o2i(off)];
4605 if (capid == PCI_EXTCAPLIST_CAP(rval)) {
4623 pcireg_t rval;
4629 rval = regs[o2i(off)];
4630 if (rval == 0xffffffff || rval == 0)
4641 foundcap = PCI_EXTCAPLIST_CAP(rval);
4649 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval));
4651 off = PCI_EXTCAPLIST_NEXT(rval);
4658 rval = regs[o2i(off)];
4676 rval = regs[o2i(off)];
4677 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0)
4688 pci_conf_print_ssr(pcireg_t rval)
4692 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */
4693 onoff("66 MHz capable", rval, __BIT(5));
4694 onoff("User Definable Features (UDF) support", rval, __BIT(6));
4695 onoff("Fast back-to-back capable", rval, __BIT(7));
4696 onoff("Data parity error detected", rval, __BIT(8));
4699 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9));
4716 onoff("Signalled target abort", rval, __BIT(11));
4717 onoff("Received target abort", rval, __BIT(12));
4718 onoff("Received master abort", rval, __BIT(13));
4719 onoff("Received system error", rval, __BIT(14));
4720 onoff("Detected parity error", rval, __BIT(15));
4731 pcireg_t rval;
4745 rval = regs[o2i(PCI_SUBSYS_ID_REG)];
4746 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
4747 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
4749 rval = regs[o2i(PCI_MAPREG_ROM)];
4750 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval);
4751 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval));
4752 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE);
4754 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) {
4785 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL));
4795 rval = regs[o2i(PCI_INTERRUPT_REG)];
4796 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval));
4797 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval));
4798 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
4799 switch (PCI_INTERRUPT_PIN(rval)) {
4820 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
4831 pcireg_t rval, csreg;
4851 rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
4853 PCI_BRIDGE_BUS_NUM_PRIMARY(rval));
4855 PCI_BRIDGE_BUS_NUM_SECONDARY(rval));
4857 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval));
4859 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval));
4861 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
4862 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16)));
4866 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff);
4867 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff);
4868 if (PCI_BRIDGE_IO_32BITS(rval))
4872 onoff("32bit I/O", rval, use_upper);
4873 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval);
4874 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval);
4876 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)];
4877 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE);
4878 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT);
4895 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)];
4898 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE));
4900 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT));
4901 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval);
4902 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval);
4909 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)];
4912 (rval >> 0) & 0xffff);
4914 (rval >> 16) & 0xffff);
4921 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval))
4925 onoff("64bit memory address", rval, use_upper);
4926 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval);
4927 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval);
4952 rval = regs[o2i(PCI_INTERRUPT_REG)];
4954 (rval >> 0) & 0xff);
4956 (rval >> 8) & 0xff);
4957 switch ((rval >> 8) & 0xff) {
4978 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)];
4980 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL));
4981 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE);
4982 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR);
4983 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA);
4984 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA);
4989 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0)
4991 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16);
4992 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT);
4993 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR);
4994 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B);
4995 onoff("Primary Discard Timer", rval,
4998 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER);
4999 onoff("Discard Timer Status", rval,
5001 onoff("Discard Timer SERR# Enable", rval,
5012 pcireg_t rval;
5031 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)];
5034 PCI_CAPLIST_PTR(rval));
5037 PCIREG_SHIFTOUT(rval, __BITS(15, 0)));
5038 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16)));
5040 rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
5042 (rval >> 0) & 0xff);
5044 (rval >> 8) & 0xff);
5046 (rval >> 16) & 0xff);
5048 (rval >> 24) & 0xff);
5064 rval = regs[o2i(PCI_INTERRUPT_REG)];
5066 (rval >> 0) & 0xff);
5068 (rval >> 8) & 0xff);
5069 switch ((rval >> 8) & 0xff) {
5090 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff;
5091 printf(" Bridge control register: 0x%04x\n", rval);
5092 onoff("Parity error response", rval, __BIT(0));
5093 onoff("SERR# enable", rval, __BIT(1));
5094 onoff("ISA enable", rval, __BIT(2));
5095 onoff("VGA enable", rval, __BIT(3));
5096 onoff("Master abort mode", rval, __BIT(5));
5097 onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
5098 onoff("Functional interrupts routed by ExCA registers", rval,
5100 onoff("Memory window 0 prefetchable", rval, __BIT(8));
5101 onoff("Memory window 1 prefetchable", rval, __BIT(9));
5102 onoff("Write posting enable", rval, __BIT(10));
5104 rval = regs[o2i(0x40)];
5105 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
5106 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));