s/Resorce/Resource/ in comment and log message.

fix typos in comments.

Fix typo. Found by rillig. s/vendor specific/vendor-specific/

Decode SCSI programming interface. Whitespace fix.

Add three new extended capabilities:

- Physical Layer 32.0 GT/s
- Alternate Protocol
- System Firmware Intermediary

place additional parens around multiline string constant to appease clang

Two fixes:

- Fix previous again. The missing comma is intended to split the long line.
- Add missing right parenthesis.

Add missing comma. Found by tnn@.

Print Physical Layer 16.0 GT/s and Lane Margining at the Receiver extended cap.

- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Rename pcie_link_compliance_preset_deemphasis to
pcie_link_preset_preshoot_deemphasis because the table is referenced from
multiple places.
- Print "reserved" instead of "unknown" when printing equalization preset.
One of them is known to be the default value.
- Rename PCI_EXTCAP_PYSLAY_16GT to PCI_EXTCAP_PL16G.

%hhx -> %x

Decode link control2's Compliance Preset/De-emphasis more. Fix typo.

fix various typos in comments, log messages and documentation.

Use PCI-SIG official acronyms:

- RP stands for Root Port.
- RC stands for Root Complex.
- RCIEP stands for Root Complex Integrated End Point.

Add Some PCI config information:

- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)

add 32.0GT/s to the list of pcie speeds (PCIe 5.x.)

fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

s/Windw/Window/ in log message.

s/Precision Time Management/Precision Time Measurement/

Rework the xxxVERBOSE option to share the common module-hook-based
verbose mechanism with MIIVERBOSE. This reduces some duplicated code
and allows us to once again permit auto-unload of MIIVERBOSE.

Change details:
* Update dev/devlist2h.awk to accomodate miidevs, including generation
of MII_STR_oui_model definitions and use of oui and model rather than
vendor and product. This also changes the compressed data in the
xxxdevs_data.h files to uint32_t (since mii oui's are up to 6 hex
digits long)
* Update a couple of phy drivers to use new calls to get verbose data
* Regen all of the xxxdevs{,_data}.h files (separate commit, coming
very soon)
* Update mii/mii_verbose.[ch] and mii/mii_physubr.c to use the various
DEV_VERBOSE_xxx macros
* Update the pci, usb, and hdaudio code as needed, to #include the
xxxdevs.h files (in order to get the proper printf format strings)
* Since dev/dev_verbose.c now uses non-literal printf format strings,
(to deal with the vendor/product vs oui/model issue), we need to
make sure it gets compiled with -Wno-error=format-nonliteral, even
in userland's libpci and librumpdev!
* Bump kernel version for the change in module interfaces

Welcome to 9.99.86!

XXX It might be useful in the future to extend the MII_STR_oui_model
XXX definitions to PCI as well (and perhaps USB and HDAUDIO). This
XXX would allow for a single centralized location for the products'
XXX descriptions, rather than being dispersed among individual
XXX drivers' xxx_match tables.

branches: 1.225.4;
Introduce autoconfiguration helpers based around device_compatible_entry:
- pci_compatible_match(): matches against the PCI ID.
- pci_compatible_match_subsys(): matches against PCI SUBSYS ID.
- pci_compatible_lookup(): look up entry by PCI ID.
- pci_compatible_lookup_subsys(): look up entry by PCI SUBSYS ID.
- pci_compatible_lookup_id(): look up entry by an arbitrary ID using the
PCI ID code conventions.

- Define PCI_COMPAT_EOL as a compat data array sentinel.

branches: 1.224.2;
change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack

Fix all the random __SHIFTOUT casts by introducing an intermediate macho,
and then deleting and fixing the rest.

branches: 1.222.2;
When parsing Enhanced Allocation entries, use the correct calulation for
finding the next entry.

Add PCIe 4.0 stuff a little:

- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.

- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
bit.
- Avoid using magic number.

Fix a bug that the virtual channel extended configuraton's arbitration phase
register can't be decoded correcty. Found by jmcneill.

branches: 1.218.2;
s/enalbe/enable/

Print some DPC register values not with %04x but with %08x because those
are 32bit.

Whitespace fixes. No functional change.

branches: 1.215.2;
Remove whitespace for consistency.

Print extend capability from 0x25 to 0x29 correctly.

Identify 16GT/s.

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

Typo (s/vaule/value/)

Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.

Add new macro PCIE_HAS_ROOTREGS(pcie_devtype) and use it. No functional
change.

The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:

Decode PCI Enhanced Allocation.

Don't print extra newline if the PCI extended configuration space doesn't exist.

- Don't print TPH requester's ST Table Size if the ST table location field
is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicaple
for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.

Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
register.

Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.

- Print Power Management Control/status register in 32bit.
- Simplify.

branches: 1.201.2;
Fix typo. s/TPL/TLP/

branches: 1.200.2;
- Add PCie Link Activation ECN.
- Use macro.
- KNF.

Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
because it's not used.
- Remove unsed code.

"s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.

Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.

NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.

Whitespace fix.

Print Error Source Identification register correctly.

Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.

IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x

Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".

- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.

- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.

Fix printf format/argument.

Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.

For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.

For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.

Tested with BCM5709:
- Target Link Speed: unknown value (0)
+ Target Link Speed: 2.5GT/s

Fix to print the following bit fields correctly.
- Supported Link Speeds Vector in LCAP2
- Lower SKP OS Generation Supported Speed Vector in LCAP2
- Lower SKP OS Reception Supported Speed Vector in LCAP2
- Enable Lower SKP OS Generation Vector in LCTL3

Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
- Maximum Link Speed in LCAP
- Current Link Speed in LCSR
- Target Link Speed in LCSR2

Add missing return to print the Slot Power Limit Value correctly.

branches: 1.183.2;
Print MSI Message data in 32bits when the Extended Message Data Capable bit
is set.

Decode TPH Requester Control register.

- The Captured Slot Power Limit value is only for device which has upsteam
port.
- The following three registers are the same encoding, so use the same
function:
- the Captured Slot Power Limit in the Device Capability register of PICe
capability.
- the Slot Power Limit in Slot Capability register of PCIe capability.
- the Base Power and Data Scale in the Data Register of Power Budgeting
capability.
- Fix the alternative encoding check of power limit as document. Add check if
scale equals to 0.

A device except Root Complex integrated has a link, so print link related
registers on device except Root Complex Integrated Endpoint and Root Complex
Event Collector.

Check slot registers if a device is PCI/PCI-X to PCI Express Bridge. Tested
with Pericom Semiconductors(Diodes) PI7C9X111SL PCIe to PCI Reverse Bridge.

branches: 1.178.2;

For want of a comma, the compiler was lost.

Add Flattening Portal Bridge capability ID and Hierarchy ID extended
capability ID.

Add Downstream Port Containment (DPC) ECN and Enhanced DPC(eDPC) ECN.

Add 0x for register output.

Add missing ':'

Use macro. No functional change.

Fix typos:
- s/Readness/Readiness/
- s/Presense/Presence/
- s/supportted/supported/
- s/Rquester/Requester/
- s/Check Enab/Check Enable/

Fix a bug that SR-IOV's system page size was doubled. ffs()'s bit are
numbered starting from 1.

Use macro. No functional change.

Use correct macro "PCI_SATA_REV" instead of PCI_MSIX_CTL for SATA revision
register. This is not a real bug because PCI_SATA_REV and PCI_MSIX_CTL have
the same value.

Don't print BAR's window size on pcictl pciN dump again
because there is no way to know it's correct value from
userland now.

- Don't try to sizing a BAR not if a device is host bridge but a device's
PCI_COMMAND_MEM_ENABLE is set.
- Fix 17 years old bug that all effective BARs are marked "not sized" on
pcictl pciN dump.
- Print BAR's window size on pcictl pciN dump.
- remove extra "(?)"

ECN: Change Root Complex Event Collector Class Code
- Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type in PCIe
extend capability to know whether it's RCEC or IOMMU.

Pint PCI Interface name if available.

Add two new PCI classes:
- processing accelerators
- non-essential instrumentation

No functional change:
- modify variable names
- KNF

fix printf formats (clang build)

Decode AGP capability.

- Fix the base power's value in the power budget capability.
- Fix typo (s/Maximun/Maximum/)

Use macro. KNF. No functional change.

Fix 0x%u...

- Print Data Select and Data Scale in pci_conf_print_pcipm_cap().
- The Message Data register of MSI cap is not 32bit but 16bit.
- When the PCIE_LCAP_MAX_SPEED bitfiled is 0, it means it supports 2.5GT/s only.
- Print link de-emphasis value by "-X dB".
- Print Completion Timeout Ranges Supported filed with alphabets.
- Print TPH Completer Supported fileld's meaning.
- Print PCIE_DCAP2_MAX_EETLP correctly. 0 means 4 End-End TLP Prefixes.
- If the Supported Link Speed Vector is 0, the Link Capability 2 register is not
implemented. Don't decode LCAP2 when the vector is 0.
- The ACS's Egress Control Vector is 32bit, so print with 0x%08x.
- Print SR-IOV's device ID.
- Use __SHIFTOUT() to avoid using magic number.
- Prefix "0x" for hexadecimal value.

branches: 1.156.2;
The Power Controller Control bit (PCIE_SLCSR_PCC) in the Slot Control & Status
Register is 0 on power on. Print "Power <on|off>" instead of "<on|off>".

Protect against buffer overflow.

Stopgap fix for in-kernel compilation (differences between humanize_number(3)
and humanize_number(9)), ok: msaitoh

Decode Resizable BAR.

- pci_conf_print_pwrbdgt_base_power(): From 0xf3 to 0xff of the Base power are
reserved above 300W (PCI 3.0 Errata).
- Emergency Power Reduction mechanism with PWRBRK signal ECN.
- Extended Message Data for MSI ECN.
- Fix typo in comment.

Add VF Resizable BARs ECN.

Don't follow an incorrect pointer in an extended capability header. Tested
with Super Micro X10SDV-8C-TLN4F bus 255, device 12, function 0 (BIOS 1.1b).

Add Dynamic Power Allocation (DPA) ECN support.

branches: 1.148.2;
B260 "Slot Power Limit" ECN. PCIe 3.1 ECN. September 18, 2015.

Add Precision Time Management (PTM) ECN.

- Add the Auto Slot Power Limit Disable bit in Slot Control register and
the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)

- ARI's function group is not bit 32-24 but 22-20.
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
Response PASID Required bit in the Page Request status register (ECN: PASID
Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()

No functional change:
- Add comments.
- Remove obsolete comment.
- Move definitions to better location.
- Rename bit definition.
- KNF.
- Indent.

Define PCIE_XCAP_{VER,TYPE}(x) and use them.

Fix register offset to print HyperTransport registers correctly.

- Restore pci_subr.c rev. 1.135's change in pci_conf_print_caplist().
As wrote in the comment, HyperTransport capability appears multiple times.
pci_conf_cap() reruns only the first entry, so it can't be used here.
- Try to decode HyperTransport capability. Currently, the capability type
of each HyperTransport capability is printed and only the MSI Mapping
capability is decoded.
- Style change.

- Move PCI_INTRSTR_LEN from pcireg.h to pcivar.h.
- In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock
frequency and Max clock period.
- In SATA cap, print register location correctly.
- In Virtual Channel cap, print reference clock with "ns".
- In Root Complex Link Declaration, print Link Entry number.

Fix compile error...

Decode SATA Capability and Multicast Extendeded Capability.

Fix format string.

Fix a bug that the TPH ST Table is wrongly decoded. Found by llvm.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

Add NVMe.

branches: 1.133.2;
Add PCIe CRS Software Visibility bit.

- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.

Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.

Fix typo in comment.

s/genric/generic/

- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.

Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().

Merge the 3 copies of devlist2h.awk that deal with 16 bit key and value
pairs to the compressed one that matt wrote.

Don't use class or typename as a variable name.

branches: 1.124.2;
Add IOMMU and the Root Complex Event Collector.

- Remove some obsoleted comments.
- KNF.

- Add PCI-X capability stuff.
- remove extra ':' in pci_conf_print_pcie_cap()
- Add comments.

Print "range: not set" if the decode window isn't set.

- Add some register definition for MSI and MSI-X
- print MSI-X capability

Do not crash if subclassp == NULL, seen while attaching rstx(4) which
match PCI_CLASS_UNDEFINED class.

Print some PCI Capabilities:
- Vendor specific (ID:0x09)
- Debugport (ID:0x0a)
- Subsystem (ID:0x0d)
- PCI Advanced Features (ID:0x13)

- Decode the programming interface field in the Class Code register and print
it.
- Print the cache line size in bytes.
- Print the Link Status 2 register itself.
- Some bits were not printed if the bit is 0. Always print them using with
onoff() macro.
- Print more bits.
- KNF.
- Use macro.
- Add comments.

- Fix calculation of supported max payload size in PCIe device capability
register.
- Fix for PCIE_SLCSR_DLLSCE flag.
- invert PCIE_SLCSR_PCC

No functional change:
- KNF
- Sort in PCI capability ID order.
- Add comments.

- Add some register definitions (subclass, power management, etc.)
- Print some information (subclass, power management)
- Use macro.

PME# clock is not bit 2 but bit 3. Use the macro!

Use onoff() macro.

Print 32bit I/O region flag and 64bit memory region flag.

Print the range of I/O, non-prefechable memory and prefechable memory.

Use macro.

Fix newline problem which was added in previous commit.

Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.

branches: 1.106.2;
One more Gb/s -> GT/s fix.

branches: 1.105.4;
- Print PCIe 2.0 or higher capability registers.
- Print Link related registers only if the device is PCI Express Endpoint,
Legacy PCI Express Endpoint or Root Port of PCI Express Root Complex.
- Don't print Root related registers if the device is Root Complex
Integrated Endpoint and print if the device is Root Complex Event Collector.
- Not Gb/s but GT/s.

- Add some PCIe 2.0 or higher capability register definitions.
- Rename some registers.
- Add comments.
- Indent.

Delete "PCI_" from PCIX and PICE capability registers.

Don't check whether PCIe Slot Control Register is all 0 or not.
For example, 82801I PCI Express Port #1 (devid 0x2940) is really
Root Port and it has the Root Control Register and the default
value is 0 (the document say so and really 0 (Tested with my
machine)).

- Add slot related registers
- Add root port related registers
- Fix the definition of PCI_PCIE_SLCAP_PSN
- Cleanup

Add PCI_CAP_SUBVENDOR (= 0x0d).

Decode some PCIe capability register bits.

Use macro.

Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded. The bit field is not 0x4e000000 but 0x3e000000.

Print some PCIE device type.

split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

Add NVM to the pci mass storage subclass

add an entry for subclass HD audio.

branches: 1.92.2;
print correct link speed for PCIexpress Gen2+
(the decoding code needs to be rewritten, sorry for only adding to
the mess)

Use an unsigned value to hold the pci_class

branches: 1.90.2;
extend the pci_aprint_devinfo slightly to cover the cases commonly
used by drivers: a short name for the quiet/naive case and a string
to override the "pcidevs" based name by one provided by the driver,
ride on yesterday's kernel minor version bump

put printing of the pci_devinfo into its own function (not inlined
by purpose) - this is a stack hog, and with this change my uTCA amd64
system boots again
a lot of similar code can be eliminated from pci device drivers this way,
but before doing so (and making the new function part of the module API)
I'd like to consider a modification to make it work with drivers which
prefer to print names from other sources (like pciide)

branches: 1.88.2; 1.88.6;
Redefine PCI_MSI_* and PCI_PCIE_* constants in terms of bits(3).

Use named constants and more conventional variable names in
pci_msi_establish() and pci_msi_disestablish(). Fix a couple of bugs:
pci_msi_establish() returned a pointer to the struct intrhand instead of
to the struct msi_hdl as it was intended to, and pci_msi_disestablish()
did not free(9) the msi_hdl.

Add two new capabilities(PCI_CAP_SATA and PCI_CAP_PCIAF).

branches: 1.86.6;
Add code to display MSI capabilities.

Update the various xxx_verbose modules to conform to the module subsystem's
new locking protocol.

Move setting of pci_verbose_loaded flag into the module's init routine.
This ensures that the flag is set even if the module was manually loaded
by the user rather than just auto-loaded.

Update pciverbose module to use module_autoload() rather than module_load().
Load the module right before each attempt to use its features, and let the
module subsystem handle unloading.

Do not try to unload the pciverbose module if it had never been loaded.

Rework the pciverbose module dispatch vectors to avoid renaming the
externally-visible entrypoint name. Also this avoids a potential
need to bump kernel version.

Requested by dyoung@ and mrg@

Extract the vendor/product tables and related access routines into a
separate kernel module. Update pci bus attach routine to load the
module (if available) when we're about to start scanning the bus, and
unload the module after the scan is finished.

On architectures which support loading of modules by the boot loader,
the 'pciverbose' module can be loaded and executed without needing to
rebuild the kernel. On all architectures, using 'options PCIVERBOSE'
in the kernel configuration file will create a 'builtin' module which
is functionally equivalent to previous behavior.

XXX Although not nearly as large as the vendor and product tables,
XXX the PCI class and subclass tables might also be offloaded into
XXX the module at a future time.

XXX Cardbus (and possibly other) drivers should also be modified to
XXX load the module before scanning/attaching devices.

branches: 1.79.2;
Extract both instances of the code that prints the PCI Secondary Status
Register into a subroutine. Use terminology similar to that which
PCI System Architecture (4th Edition) uses. For comparison with PCI
reference books, specify flags and fields with __BIT(n) and __BITS(m, n)
instead of hexadecimal constants.

branches: 1.78.2;
fix some bitmask in PCI Express capabilities decoding
being here, fix some typos and add a comma for clarity

Decode and display PCI Power Management registers when available.

Store pcidevs in a more compact manner. Instead of many string with duplicate
words, store each word individual in a long string and then store offsets
in the string to that word. This reduces the space needed by half.

branches: 1.75.6; 1.75.8; 1.75.10;
Oh, so that's how you spell Legacy -- thanks spellcheck!

branches: 1.74.2; 1.74.4;
use aprint_*_dev and device_xname

branches: 1.73.16;
machine/{bus,cpu,intr}.h -> sys/{bus,cpu,intr}.h

branches: 1.72.2;
Add some basic parsing of the PCI Express capabilities register.
This is enough to help detect the source of interrupt storms at least
for my Thinkpad.

branches: 1.71.8; 1.71.22; 1.71.24; 1.71.26;
__unused removal on arguments; approved by core.

while we are here, also print the interrupt disable bit
in VERBOSE/pcictl

now that we have -Wno-unused-parameter, back out all the tremendously ugly
code to gratuitously access said parameters.

more __unused

more unused variable fallout.

- sprinkle __unused on function decls.
- fix a couple of unused bugs
- no more -Wno-unused for i386

branches: 1.65.2; 1.65.4;
add missing initializers

-add 2 subclasses new in rev. 3.0 of the spec, and fix a pasto in another
-get power management rev printing right

branches: 1.63.4; 1.63.6; 1.63.8; 1.63.14;
merge ktrace-lwp.

Only include <sys/systm.h> if _KERNEL is defined.

branches: 1.61.2; 1.61.4;
Use ANSI function decls and static.

nuke trailing whitespace

branches: 1.59.4; 1.59.6;
For the PCIVERBOSE case, separate vendors and products into separate tables.
Eliminating redundant pointers in the tables saves nearly 20K (20% of the table
size). In the process, add a pci_findproduct() and make that and
pci_findvendor() return a "const char *".

pass string length (= boundary info) to pci_devinfo so that we do not run over
the end of memory region

Use the right bits for the AGP version.

branches: 1.56.2;
Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

fix typo in comment

Quell an uninitialised variable warning.

call the capability list ptr by its name

correct caplist head for Cardbus bridges

-corrected "MSI" capability
-added some new subclasses and capabilities
-move capability list printing into a separate function and call it
for each header type (not type 0 only)

Fortunately for us, all interrupt controllers are not 8259's

branches: 1.49.2;
Make pci_conf_print() dump the device-dependent header in userspace, too.

iadd subclass codes from the 2.3 spec

add RCSID

Include stdio.h when compiled in userland to pull in declaration of printf etc.

Allow this file to be used in userspace, as well.

ANSI'ify.

Fix sample code in comment; pci_conf_print() takes three arguments.

branches: 1.42.2; 1.42.4; 1.42.6;
adapt to pci_knowndevs[] being const, make local constant arrays const

s/iRDA/IrDA/

Update for current PCI device class/subclass and capability codes.
(also, tweak the I2O subclass string to be "standard" -- the removal
of version info didn't extend that far.)

I2O subclasses currently have nothing to do with the protocol version.

don't attempt to size Host Bridge BARs. (it's a good way to die.)
provide a clue about 16-bit vs. 32-bit I/O BARs.

When performing pci_config_dump:
- Display the full value of 64-bit BARs.
- Avoid displaying the upper 32 bits of 64-bit BARs as a separate 32-bit BAR.

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

branches: 1.35.4;
opt_pciverbose.h -> opt_pci.h (it's gonna be used by more things, soon)

use BUS_SPACE_MAP_PREFETCHABLE instead BUS_SPACE_MAP_CACHEABLE where the
PCI BAR bit is referred to

Report the Capability List support bit of the SR and, if set, print the
the Capability list pointer register as such as well as the capabilities
implemented in the list.

branches: 1.32.2; 1.32.8;
add classes/subclasses new in PCI 2.2. Needs a bit of cleanup, but then,
so does everything involving configuration space headers and if i don't
get this out of my source tree i'll go insane.

use a symbolic definition for the PCI subsystem ID

Make copyright notices with my name consistent.

Add USB support. Supported so far:
* UHCI and OHCI host controllers on PCI
* Hubs
* HID devices withe special drivers for mouse and keyboard
* Printers

factor out some common code, and enhance functionality slightly: allow
the BAR-printing function to print a name for the register, factor out
a common register-bits function which can handle the fact that type 2
headers have a different size than is usual, and actually do something
useful with the rest of the bits in the type 2 header.

Clean up slightly, abstract pci_conf_print family's base address register
printing into a function, add a bit more pretty-printing of existing stuff.
Implement pretty-printers for type 1 and type 2 headers. (Right now,
these are just quick stabs based on some on-line bridge docs that I have
handy on my laptop. Mmmm, meetings. I'll check the bits when I get
back within reach of my official docs.)

largely reimplement pci_conf_print():
* print all configuration space registers. Then, where possible,
interpret them. (That is, PRESENT ALL THE DATA, then interpret it --
don't hide data behind interpretation. Also, when interpreting
fields, try to print out the specific value that's being interpreted.)
* handle different header types.
* allow caller to specify a function which can interpret the
device-dependent header and is responsible for pretty-printing it.

It spews (use 'options MSGBUFSIZE=...' 8-), but when you want the data,
you really want _all_ of it.

Still needs some cleanup and additional code (e.g. interepretation
of PCI-PCI (type 1) and PCI-Cardbus (type 2(?)) bridge headers).

In pci_conf_print(), don't print a mapping register if the size is 0.

Properly compute the region sizes in pci_conf_print(). Bug pointed out
by Chris Demetriou.

Avoid "unused variable" warning without PCIVERBOSE.
From mynhier@cs.utk.edu (PR kern/5328).

Add pci_conf_print(), a function to dump the PCI configuration space, useful
in driver debugging. From Zubin D. Dittia <zubin@clouseau.arl.wustl.edu>,
PR #4249.

Declare PCIVERBOSE by defopt in files.pci. Include opt_pciverbose.h
in pci_subr.c.

branches: 1.20.4;
fix multi-function device support, add new known classes/subclasses,
and clean up class/subclass printing. From brb@brig.com via PR 3359.

backout kprintf changes

printf -> kprintf, sprintf -> ksprintf

remove some colons to be slightly more friendly to things trying to
parse autoconfiguration output.

oops; spaces -> tabs

if not PCIVERBOSE, don't say that vendor/product is "unknown," just say
what it is.

make PCI bus match/attach and sub-device attachment machine-independent.

update PCIVERBOSE code in various ways:
(1) remove the 'UNSUPP' keyword from the device list,
because it can't be reasonably used (becuase different
devices may be supported on different machines, for
good reason).
(2) enhance pci_devinfo so that class/subclass information
is optional (so pci_devinfo can be used by drivers that
match classes of devices, and want to look up the
devices' names easily).
(3) more known vendors and devices.

check for null subclass pointer. From Todd Mummert

fix reference to incorrect struct (paste-o)

define and call "pci_devinfo()", which creates a string from the
vendor & product IDs and class information, which is printed if device
isn't found. Optionally (via "PCIVERBOSE" option) does table lookup
to try to see if it knows what the device really is (informational only...).

more appropriate name, as this only has PCI support subroutines.

split single-subdevice lookup & attachment into a subroutine
(pci_attach_subdev()). remove pciattach() function and the pcicd cfdriver
struct, the former because thre are a lot of attachment actions which really
are machine-dependent (perhaps even "most"), and the latter because now that
both pcimatch() and pciattach() are machine-dependent it's bad style to
declare them here and it gains nothing.

include files from the correct places.

Make a wrapper match function to check the bus and device numbers, rather
than insisting that every driver do it.

Rename pciprobe() to pcimatch(), and move it to pci_machdep.c.

Always use direct configuration.

new RCS ID format.

Update some comments.

branches: 1.1.2;
Add PCI autoconfiguration support.

fix typos in comments.

Fix typo. Found by rillig. s/vendor specific/vendor-specific/

Decode SCSI programming interface. Whitespace fix.

Add three new extended capabilities:

- Physical Layer 32.0 GT/s
- Alternate Protocol
- System Firmware Intermediary

place additional parens around multiline string constant to appease clang

Two fixes:

- Fix previous again. The missing comma is intended to split the long line.
- Add missing right parenthesis.

Add missing comma. Found by tnn@.

Print Physical Layer 16.0 GT/s and Lane Margining at the Receiver extended cap.

- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Rename pcie_link_compliance_preset_deemphasis to
pcie_link_preset_preshoot_deemphasis because the table is referenced from
multiple places.
- Print "reserved" instead of "unknown" when printing equalization preset.
One of them is known to be the default value.
- Rename PCI_EXTCAP_PYSLAY_16GT to PCI_EXTCAP_PL16G.

%hhx -> %x

Decode link control2's Compliance Preset/De-emphasis more. Fix typo.

fix various typos in comments, log messages and documentation.

Use PCI-SIG official acronyms:

- RP stands for Root Port.
- RC stands for Root Complex.
- RCIEP stands for Root Complex Integrated End Point.

Add Some PCI config information:

- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)

add 32.0GT/s to the list of pcie speeds (PCIe 5.x.)

fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

s/Windw/Window/ in log message.

s/Precision Time Management/Precision Time Measurement/

Rework the xxxVERBOSE option to share the common module-hook-based
verbose mechanism with MIIVERBOSE. This reduces some duplicated code
and allows us to once again permit auto-unload of MIIVERBOSE.

Change details:
* Update dev/devlist2h.awk to accomodate miidevs, including generation
of MII_STR_oui_model definitions and use of oui and model rather than
vendor and product. This also changes the compressed data in the
xxxdevs_data.h files to uint32_t (since mii oui's are up to 6 hex
digits long)
* Update a couple of phy drivers to use new calls to get verbose data
* Regen all of the xxxdevs{,_data}.h files (separate commit, coming
very soon)
* Update mii/mii_verbose.[ch] and mii/mii_physubr.c to use the various
DEV_VERBOSE_xxx macros
* Update the pci, usb, and hdaudio code as needed, to #include the
xxxdevs.h files (in order to get the proper printf format strings)
* Since dev/dev_verbose.c now uses non-literal printf format strings,
(to deal with the vendor/product vs oui/model issue), we need to
make sure it gets compiled with -Wno-error=format-nonliteral, even
in userland's libpci and librumpdev!
* Bump kernel version for the change in module interfaces

Welcome to 9.99.86!

XXX It might be useful in the future to extend the MII_STR_oui_model
XXX definitions to PCI as well (and perhaps USB and HDAUDIO). This
XXX would allow for a single centralized location for the products'
XXX descriptions, rather than being dispersed among individual
XXX drivers' xxx_match tables.

branches: 1.225.4;
Introduce autoconfiguration helpers based around device_compatible_entry:
- pci_compatible_match(): matches against the PCI ID.
- pci_compatible_match_subsys(): matches against PCI SUBSYS ID.
- pci_compatible_lookup(): look up entry by PCI ID.
- pci_compatible_lookup_subsys(): look up entry by PCI SUBSYS ID.
- pci_compatible_lookup_id(): look up entry by an arbitrary ID using the
PCI ID code conventions.

- Define PCI_COMPAT_EOL as a compat data array sentinel.

branches: 1.224.2;
change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack

Fix all the random __SHIFTOUT casts by introducing an intermediate macho,
and then deleting and fixing the rest.

branches: 1.222.2;
When parsing Enhanced Allocation entries, use the correct calulation for
finding the next entry.

Add PCIe 4.0 stuff a little:

- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.

- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
bit.
- Avoid using magic number.

Fix a bug that the virtual channel extended configuraton's arbitration phase
register can't be decoded correcty. Found by jmcneill.

branches: 1.218.2;
s/enalbe/enable/

Print some DPC register values not with %04x but with %08x because those
are 32bit.

Whitespace fixes. No functional change.

branches: 1.215.2;
Remove whitespace for consistency.

Print extend capability from 0x25 to 0x29 correctly.

Identify 16GT/s.

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

Typo (s/vaule/value/)

Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.

Add new macro PCIE_HAS_ROOTREGS(pcie_devtype) and use it. No functional
change.

The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:

Decode PCI Enhanced Allocation.

Don't print extra newline if the PCI extended configuration space doesn't exist.

- Don't print TPH requester's ST Table Size if the ST table location field
is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicaple
for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.

Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
register.

Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.

- Print Power Management Control/status register in 32bit.
- Simplify.

branches: 1.201.2;
Fix typo. s/TPL/TLP/

branches: 1.200.2;
- Add PCie Link Activation ECN.
- Use macro.
- KNF.

Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
because it's not used.
- Remove unsed code.

"s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.

Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.

NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.

Whitespace fix.

Print Error Source Identification register correctly.

Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.

IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x

Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".

- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.

- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.

Fix printf format/argument.

Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.

For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.

For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.

Tested with BCM5709:
- Target Link Speed: unknown value (0)
+ Target Link Speed: 2.5GT/s

Fix to print the following bit fields correctly.
- Supported Link Speeds Vector in LCAP2
- Lower SKP OS Generation Supported Speed Vector in LCAP2
- Lower SKP OS Reception Supported Speed Vector in LCAP2
- Enable Lower SKP OS Generation Vector in LCTL3

Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
- Maximum Link Speed in LCAP
- Current Link Speed in LCSR
- Target Link Speed in LCSR2

Add missing return to print the Slot Power Limit Value correctly.

branches: 1.183.2;
Print MSI Message data in 32bits when the Extended Message Data Capable bit
is set.

Decode TPH Requester Control register.

- The Captured Slot Power Limit value is only for device which has upsteam
port.
- The following three registers are the same encoding, so use the same
function:
- the Captured Slot Power Limit in the Device Capability register of PICe
capability.
- the Slot Power Limit in Slot Capability register of PCIe capability.
- the Base Power and Data Scale in the Data Register of Power Budgeting
capability.
- Fix the alternative encoding check of power limit as document. Add check if
scale equals to 0.

A device except Root Complex integrated has a link, so print link related
registers on device except Root Complex Integrated Endpoint and Root Complex
Event Collector.

Check slot registers if a device is PCI/PCI-X to PCI Express Bridge. Tested
with Pericom Semiconductors(Diodes) PI7C9X111SL PCIe to PCI Reverse Bridge.

branches: 1.178.2;

For want of a comma, the compiler was lost.

Add Flattening Portal Bridge capability ID and Hierarchy ID extended
capability ID.

Add Downstream Port Containment (DPC) ECN and Enhanced DPC(eDPC) ECN.

Add 0x for register output.

Add missing ':'

Use macro. No functional change.

Fix typos:
- s/Readness/Readiness/
- s/Presense/Presence/
- s/supportted/supported/
- s/Rquester/Requester/
- s/Check Enab/Check Enable/

Fix a bug that SR-IOV's system page size was doubled. ffs()'s bit are
numbered starting from 1.

Use macro. No functional change.

Use correct macro "PCI_SATA_REV" instead of PCI_MSIX_CTL for SATA revision
register. This is not a real bug because PCI_SATA_REV and PCI_MSIX_CTL have
the same value.

Don't print BAR's window size on pcictl pciN dump again
because there is no way to know it's correct value from
userland now.

- Don't try to sizing a BAR not if a device is host bridge but a device's
PCI_COMMAND_MEM_ENABLE is set.
- Fix 17 years old bug that all effective BARs are marked "not sized" on
pcictl pciN dump.
- Print BAR's window size on pcictl pciN dump.
- remove extra "(?)"

ECN: Change Root Complex Event Collector Class Code
- Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type in PCIe
extend capability to know whether it's RCEC or IOMMU.

Pint PCI Interface name if available.

Add two new PCI classes:
- processing accelerators
- non-essential instrumentation

No functional change:
- modify variable names
- KNF

fix printf formats (clang build)

Decode AGP capability.

- Fix the base power's value in the power budget capability.
- Fix typo (s/Maximun/Maximum/)

Use macro. KNF. No functional change.

Fix 0x%u...

- Print Data Select and Data Scale in pci_conf_print_pcipm_cap().
- The Message Data register of MSI cap is not 32bit but 16bit.
- When the PCIE_LCAP_MAX_SPEED bitfiled is 0, it means it supports 2.5GT/s only.
- Print link de-emphasis value by "-X dB".
- Print Completion Timeout Ranges Supported filed with alphabets.
- Print TPH Completer Supported fileld's meaning.
- Print PCIE_DCAP2_MAX_EETLP correctly. 0 means 4 End-End TLP Prefixes.
- If the Supported Link Speed Vector is 0, the Link Capability 2 register is not
implemented. Don't decode LCAP2 when the vector is 0.
- The ACS's Egress Control Vector is 32bit, so print with 0x%08x.
- Print SR-IOV's device ID.
- Use __SHIFTOUT() to avoid using magic number.
- Prefix "0x" for hexadecimal value.

branches: 1.156.2;
The Power Controller Control bit (PCIE_SLCSR_PCC) in the Slot Control & Status
Register is 0 on power on. Print "Power <on|off>" instead of "<on|off>".

Protect against buffer overflow.

Stopgap fix for in-kernel compilation (differences between humanize_number(3)
and humanize_number(9)), ok: msaitoh

Decode Resizable BAR.

- pci_conf_print_pwrbdgt_base_power(): From 0xf3 to 0xff of the Base power are
reserved above 300W (PCI 3.0 Errata).
- Emergency Power Reduction mechanism with PWRBRK signal ECN.
- Extended Message Data for MSI ECN.
- Fix typo in comment.

Add VF Resizable BARs ECN.

Don't follow an incorrect pointer in an extended capability header. Tested
with Super Micro X10SDV-8C-TLN4F bus 255, device 12, function 0 (BIOS 1.1b).

Add Dynamic Power Allocation (DPA) ECN support.

branches: 1.148.2;
B260 "Slot Power Limit" ECN. PCIe 3.1 ECN. September 18, 2015.

Add Precision Time Management (PTM) ECN.

- Add the Auto Slot Power Limit Disable bit in Slot Control register and
the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)

- ARI's function group is not bit 32-24 but 22-20.
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
Response PASID Required bit in the Page Request status register (ECN: PASID
Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()

No functional change:
- Add comments.
- Remove obsolete comment.
- Move definitions to better location.
- Rename bit definition.
- KNF.
- Indent.

Define PCIE_XCAP_{VER,TYPE}(x) and use them.

Fix register offset to print HyperTransport registers correctly.

- Restore pci_subr.c rev. 1.135's change in pci_conf_print_caplist().
As wrote in the comment, HyperTransport capability appears multiple times.
pci_conf_cap() reruns only the first entry, so it can't be used here.
- Try to decode HyperTransport capability. Currently, the capability type
of each HyperTransport capability is printed and only the MSI Mapping
capability is decoded.
- Style change.

- Move PCI_INTRSTR_LEN from pcireg.h to pcivar.h.
- In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock
frequency and Max clock period.
- In SATA cap, print register location correctly.
- In Virtual Channel cap, print reference clock with "ns".
- In Root Complex Link Declaration, print Link Entry number.

Fix compile error...

Decode SATA Capability and Multicast Extendeded Capability.

Fix format string.

Fix a bug that the TPH ST Table is wrongly decoded. Found by llvm.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

Add NVMe.

branches: 1.133.2;
Add PCIe CRS Software Visibility bit.

- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.

Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.

Fix typo in comment.

s/genric/generic/

- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.

Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().

Merge the 3 copies of devlist2h.awk that deal with 16 bit key and value
pairs to the compressed one that matt wrote.

Don't use class or typename as a variable name.

branches: 1.124.2;
Add IOMMU and the Root Complex Event Collector.

- Remove some obsoleted comments.
- KNF.

- Add PCI-X capability stuff.
- remove extra ':' in pci_conf_print_pcie_cap()
- Add comments.

Print "range: not set" if the decode window isn't set.

- Add some register definition for MSI and MSI-X
- print MSI-X capability

Do not crash if subclassp == NULL, seen while attaching rstx(4) which
match PCI_CLASS_UNDEFINED class.

Print some PCI Capabilities:
- Vendor specific (ID:0x09)
- Debugport (ID:0x0a)
- Subsystem (ID:0x0d)
- PCI Advanced Features (ID:0x13)

- Decode the programming interface field in the Class Code register and print
it.
- Print the cache line size in bytes.
- Print the Link Status 2 register itself.
- Some bits were not printed if the bit is 0. Always print them using with
onoff() macro.
- Print more bits.
- KNF.
- Use macro.
- Add comments.

- Fix calculation of supported max payload size in PCIe device capability
register.
- Fix for PCIE_SLCSR_DLLSCE flag.
- invert PCIE_SLCSR_PCC

No functional change:
- KNF
- Sort in PCI capability ID order.
- Add comments.

- Add some register definitions (subclass, power management, etc.)
- Print some information (subclass, power management)
- Use macro.

PME# clock is not bit 2 but bit 3. Use the macro!

Use onoff() macro.

Print 32bit I/O region flag and 64bit memory region flag.

Print the range of I/O, non-prefechable memory and prefechable memory.

Use macro.

Fix newline problem which was added in previous commit.

Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.

branches: 1.106.2;
One more Gb/s -> GT/s fix.

branches: 1.105.4;
- Print PCIe 2.0 or higher capability registers.
- Print Link related registers only if the device is PCI Express Endpoint,
Legacy PCI Express Endpoint or Root Port of PCI Express Root Complex.
- Don't print Root related registers if the device is Root Complex
Integrated Endpoint and print if the device is Root Complex Event Collector.
- Not Gb/s but GT/s.

- Add some PCIe 2.0 or higher capability register definitions.
- Rename some registers.
- Add comments.
- Indent.

Delete "PCI_" from PCIX and PICE capability registers.

Don't check whether PCIe Slot Control Register is all 0 or not.
For example, 82801I PCI Express Port #1 (devid 0x2940) is really
Root Port and it has the Root Control Register and the default
value is 0 (the document say so and really 0 (Tested with my
machine)).

- Add slot related registers
- Add root port related registers
- Fix the definition of PCI_PCIE_SLCAP_PSN
- Cleanup

Add PCI_CAP_SUBVENDOR (= 0x0d).

Decode some PCIe capability register bits.

Use macro.

Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded. The bit field is not 0x4e000000 but 0x3e000000.

Print some PCIE device type.

split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

Add NVM to the pci mass storage subclass

add an entry for subclass HD audio.

branches: 1.92.2;
print correct link speed for PCIexpress Gen2+
(the decoding code needs to be rewritten, sorry for only adding to
the mess)

Use an unsigned value to hold the pci_class

branches: 1.90.2;
extend the pci_aprint_devinfo slightly to cover the cases commonly
used by drivers: a short name for the quiet/naive case and a string
to override the "pcidevs" based name by one provided by the driver,
ride on yesterday's kernel minor version bump

put printing of the pci_devinfo into its own function (not inlined
by purpose) - this is a stack hog, and with this change my uTCA amd64
system boots again
a lot of similar code can be eliminated from pci device drivers this way,
but before doing so (and making the new function part of the module API)
I'd like to consider a modification to make it work with drivers which
prefer to print names from other sources (like pciide)

branches: 1.88.2; 1.88.6;
Redefine PCI_MSI_* and PCI_PCIE_* constants in terms of bits(3).

Use named constants and more conventional variable names in
pci_msi_establish() and pci_msi_disestablish(). Fix a couple of bugs:
pci_msi_establish() returned a pointer to the struct intrhand instead of
to the struct msi_hdl as it was intended to, and pci_msi_disestablish()
did not free(9) the msi_hdl.

Add two new capabilities(PCI_CAP_SATA and PCI_CAP_PCIAF).

branches: 1.86.6;
Add code to display MSI capabilities.

Update the various xxx_verbose modules to conform to the module subsystem's
new locking protocol.

Move setting of pci_verbose_loaded flag into the module's init routine.
This ensures that the flag is set even if the module was manually loaded
by the user rather than just auto-loaded.

Update pciverbose module to use module_autoload() rather than module_load().
Load the module right before each attempt to use its features, and let the
module subsystem handle unloading.

Do not try to unload the pciverbose module if it had never been loaded.

Rework the pciverbose module dispatch vectors to avoid renaming the
externally-visible entrypoint name. Also this avoids a potential
need to bump kernel version.

Requested by dyoung@ and mrg@

Extract the vendor/product tables and related access routines into a
separate kernel module. Update pci bus attach routine to load the
module (if available) when we're about to start scanning the bus, and
unload the module after the scan is finished.

On architectures which support loading of modules by the boot loader,
the 'pciverbose' module can be loaded and executed without needing to
rebuild the kernel. On all architectures, using 'options PCIVERBOSE'
in the kernel configuration file will create a 'builtin' module which
is functionally equivalent to previous behavior.

XXX Although not nearly as large as the vendor and product tables,
XXX the PCI class and subclass tables might also be offloaded into
XXX the module at a future time.

XXX Cardbus (and possibly other) drivers should also be modified to
XXX load the module before scanning/attaching devices.

branches: 1.79.2;
Extract both instances of the code that prints the PCI Secondary Status
Register into a subroutine. Use terminology similar to that which
PCI System Architecture (4th Edition) uses. For comparison with PCI
reference books, specify flags and fields with __BIT(n) and __BITS(m, n)
instead of hexadecimal constants.

branches: 1.78.2;
fix some bitmask in PCI Express capabilities decoding
being here, fix some typos and add a comma for clarity

Decode and display PCI Power Management registers when available.

Store pcidevs in a more compact manner. Instead of many string with duplicate
words, store each word individual in a long string and then store offsets
in the string to that word. This reduces the space needed by half.

branches: 1.75.6; 1.75.8; 1.75.10;
Oh, so that's how you spell Legacy -- thanks spellcheck!

branches: 1.74.2; 1.74.4;
use aprint_*_dev and device_xname

branches: 1.73.16;
machine/{bus,cpu,intr}.h -> sys/{bus,cpu,intr}.h

branches: 1.72.2;
Add some basic parsing of the PCI Express capabilities register.
This is enough to help detect the source of interrupt storms at least
for my Thinkpad.

branches: 1.71.8; 1.71.22; 1.71.24; 1.71.26;
__unused removal on arguments; approved by core.

while we are here, also print the interrupt disable bit
in VERBOSE/pcictl

now that we have -Wno-unused-parameter, back out all the tremendously ugly
code to gratuitously access said parameters.

more __unused

more unused variable fallout.

- sprinkle __unused on function decls.
- fix a couple of unused bugs
- no more -Wno-unused for i386

branches: 1.65.2; 1.65.4;
add missing initializers

-add 2 subclasses new in rev. 3.0 of the spec, and fix a pasto in another
-get power management rev printing right

branches: 1.63.4; 1.63.6; 1.63.8; 1.63.14;
merge ktrace-lwp.

Only include <sys/systm.h> if _KERNEL is defined.

branches: 1.61.2; 1.61.4;
Use ANSI function decls and static.

nuke trailing whitespace

branches: 1.59.4; 1.59.6;
For the PCIVERBOSE case, separate vendors and products into separate tables.
Eliminating redundant pointers in the tables saves nearly 20K (20% of the table
size). In the process, add a pci_findproduct() and make that and
pci_findvendor() return a "const char *".