dev/pci/if_ste.c

121 	bus_space_handle_t sc_sh;	/* bus space handle */
382 		sc->sc_sh = memh;
385 		sc->sc_sh = ioh;
634 		if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) &
812 		if (bus_space_read_4(sc->sc_st, sc->sc_sh,
814 			bus_space_write_4(sc->sc_st, sc->sc_sh,
817 			bus_space_write_4(sc->sc_st, sc->sc_sh,
820 			bus_space_write_4(sc->sc_st, sc->sc_sh,
895 	if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) &
900 		isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck);
919 				txstat = bus_space_read_1(sc->sc_st, sc->sc_sh,
934 					bus_space_write_1(sc->sc_st, sc->sc_sh,
938 						sc->sc_sh, STE_TxFrameId));
955 				bus_space_write_2(sc->sc_st, sc->sc_sh,
971 	bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable,
1148 	bus_space_handle_t sh = sc->sc_sh;
1197 	ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl);
1199 	bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits);
1205 		if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) &
1226 	bus_space_write_2(sc->sc_st, sc->sc_sh,
1229 	bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh,
1248 	bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0);
1249 	bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable);
1250 	bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt);
1252 	bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr,
1254 	bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume);
1267 	bus_space_handle_t sh = sc->sc_sh;
1338 	bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127);
1449 	bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0);
1454 	bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1,
1460 	bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl,
1493 		if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) &
1513 	bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl,
1518 	*data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData);
1647 		bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0,
1649 		bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1,
1651 		bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2,
1653 		bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3,
1657 	bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode,
1710 	bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0);
1723 	return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl));
1736 	bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val);