Lines Matching refs:VB
3618 /* The VB field in a VA, VX or VXR form instruction. */
3619 #define VB VA + 1
3623 #define VC VB + 1
4394 /* A VX_MASK with the VB field fixed. */
4397 /* A VX_MASK with the VA and VB fields fixed. */
5097 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5099 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5100 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5101 {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}},
5102 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5103 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5104 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5105 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5106 {"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}},
5108 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5109 {"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}},
5110 {"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}},
5111 {"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}},
5112 {"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}},
5114 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5115 {"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}},
5121 {"vsldbi", VX (4, 22), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}},
5124 {"vextdubvlx", VX (4, 24), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5127 {"vextdubvrx", VX (4, 25), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5130 {"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5132 {"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5134 {"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5136 {"vextduwvrx", VX (4, 29), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5138 {"vextddvlx", VX (4, 30), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5140 {"vextddvrx", VX (4, 31), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5142 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5143 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5144 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5145 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
5147 {"vmsumcud", VXA(4, 23), VXA_MASK, POWER10, 0, {VD, VA, VB, VC}},
5148 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5150 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5151 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5152 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5154 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5156 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5158 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5160 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5161 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
5162 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5164 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
5166 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
5180 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
5182 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5184 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5186 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5188 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5190 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5191 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5192 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5193 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5194 {"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}},
5195 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5196 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5197 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5198 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5200 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5202 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5203 {"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}},
5213 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5214 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5215 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5216 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5217 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5218 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5219 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5220 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5221 {"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}},
5222 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5223 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5224 {"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}},
5230 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5231 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5232 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5233 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5234 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5235 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5236 {"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}},
5237 {"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}},
5238 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5244 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5245 {"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {BF, VA, VB}},
5246 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5247 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5248 {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}},
5249 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5250 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5251 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5252 {"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}},
5253 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5254 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5255 {"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}},
5262 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5263 {"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {BF, VA, VB}},
5264 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5265 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5266 {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}},
5267 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5268 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5269 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5270 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5271 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5272 {"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}},
5279 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5280 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5281 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5282 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5283 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5284 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5285 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5286 {"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
5287 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5289 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5290 {"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}},
5293 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5294 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5295 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5296 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5297 {"vcmpequq", VXR(4, 455,0), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5298 {"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}},
5299 {"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}},
5300 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5301 {"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
5303 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5310 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5313 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5316 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5317 {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}},
5320 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5322 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5325 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5326 {"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}},
5329 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
5330 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5333 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5340 {"vsrdbi", VX (4, 534), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}},
5370 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5371 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5372 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5373 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5374 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5375 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5376 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5377 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
5378 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5379 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5385 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5388 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5391 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5394 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5395 {"vcmpgtuq", VXR(4, 647,0), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5397 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5399 {"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}},
5402 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5403 {"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}},
5406 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
5407 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5410 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5453 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5457 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5462 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5464 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5465 {"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}},
5468 {"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
5472 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5473 {"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
5477 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5482 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5555 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5558 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5561 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5562 {"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}},
5564 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5566 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5568 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5569 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5570 {"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}},
5573 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5576 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5607 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5608 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5609 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5610 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5611 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5612 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5613 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5614 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5616 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5617 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5625 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5626 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5627 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5628 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5629 {"vcmpgtsq", VXR(4, 903,0), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5630 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5631 {"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}},
5632 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5633 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5634 {"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}},
5636 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5640 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5641 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5642 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5643 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5644 {"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}},
5645 {"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}},
5646 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5647 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5648 {"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}},
5649 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5650 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5656 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5657 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
5658 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5659 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5661 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5662 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5663 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5667 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5670 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5673 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5674 {"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}},
5675 {"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}},
5676 {"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}},
5677 {"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}},
5692 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5693 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
5694 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5696 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5697 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5698 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5701 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5703 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5705 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5708 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5710 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5733 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5734 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5735 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5736 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5738 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5739 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5740 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5741 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5748 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5750 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
5755 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5757 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5759 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5762 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5767 {"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}},
5768 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5775 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5777 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
5779 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5783 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5787 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5790 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5791 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5794 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5806 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5808 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5810 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5813 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5817 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5819 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5821 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5825 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5826 {"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}},
5828 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5843 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5845 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5846 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5847 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5848 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5849 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5850 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5851 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5852 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5854 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5859 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5865 {"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}},
5877 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
5881 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5883 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5886 {"vcmpequq.", VXR(4, 455,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5893 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5894 {"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}},
5896 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5910 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5911 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
5912 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
5913 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5914 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5915 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5916 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5917 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5918 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5919 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5920 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5921 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5922 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5923 {"vextsd2q", VXVA(4,1538,27), VXVA_MASK, POWER10, 0, {VD, VB}},
5924 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5925 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5926 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5927 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5929 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5932 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5933 {"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}},
5934 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5935 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5937 {"vexpandbm", VXVA(4,1602,0), VXVA_MASK, POWER10, 0, {VD, VB}},
5938 {"vexpandhm", VXVA(4,1602,1), VXVA_MASK, POWER10, 0, {VD, VB}},
5939 {"vexpandwm", VXVA(4,1602,2), VXVA_MASK, POWER10, 0, {VD, VB}},
5940 {"vexpanddm", VXVA(4,1602,3), VXVA_MASK, POWER10, 0, {VD, VB}},
5941 {"vexpandqm", VXVA(4,1602,4), VXVA_MASK, POWER10, 0, {VD, VB}},
5942 {"vextractbm", VXVA(4,1602,8), VXVA_MASK, POWER10, 0, {RT, VB}},
5943 {"vextracthm", VXVA(4,1602,9), VXVA_MASK, POWER10, 0, {RT, VB}},
5944 {"vextractwm", VXVA(4,1602,10), VXVA_MASK, POWER10, 0, {RT, VB}},
5945 {"vextractdm", VXVA(4,1602,11), VXVA_MASK, POWER10, 0, {RT, VB}},
5946 {"vextractqm", VXVA(4,1602,12), VXVA_MASK, POWER10, 0, {RT, VB}},
5952 {"vcntmbb", VXVA(4,1602,24), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5953 {"vcntmbh", VXVA(4,1602,26), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5954 {"vcntmbw", VXVA(4,1602,28), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5955 {"vcntmbd", VXVA(4,1602,30), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5957 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
5958 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5959 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5962 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5963 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5964 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5966 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5967 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5969 {"vcmpgtuq.", VXR(4, 647,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5971 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5972 {"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}},
5973 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5974 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5976 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5977 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5979 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5981 {"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}},
5982 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5983 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5984 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5985 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5986 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5987 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5990 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5991 {"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}},
5992 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5995 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5996 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5997 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5998 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5999 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
6000 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
6007 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
6008 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6009 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6010 {"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}},
6011 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
6013 {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
6015 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
6016 {"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}},
6017 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
6018 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
6021 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6022 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6023 {"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}},
6024 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
6026 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
6028 {"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}},
9406 {"xxgenpcvbm", X(60,916), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9407 {"xxgenpcvhm", X(60,917), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9414 {"xxgenpcvwm", X(60,948), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9415 {"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9465 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9466 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9468 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
9469 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
9551 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9552 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9554 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
9570 {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9584 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9590 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
9609 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
9613 {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9620 {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9637 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9638 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9643 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9644 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9649 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9650 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9655 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9656 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9664 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9665 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9670 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9671 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9685 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
9690 {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9692 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
9699 {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9707 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9708 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9709 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9710 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9711 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9712 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9713 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9728 {"xscvqpuqz", XVA(63,836,0), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9729 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9730 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9731 {"xscvuqqp", XVA(63,836,3), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9732 {"xscvqpsqz", XVA(63,836,8), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9733 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9734 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9735 {"xscvsqqp", XVA(63,836,11), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9736 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9737 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9738 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9739 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9740 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9752 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9765 {"dcffixqq", XVA(63,994,0), XVA_MASK, POWER10, PPCVLE, {FRTp, VB}},