Lines Matching defs:PPC403

4963 #define PPC403	PPC_OPCODE_403
6599 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
7235 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7236 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7294 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
7350 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
7499 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
7575 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
7576 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
7577 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
7578 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
7579 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
7580 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
7581 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
7582 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
7583 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
7584 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
7585 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
7586 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
7587 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
7588 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
7589 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
7590 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
7591 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
7592 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
7593 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
7594 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
7595 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
7596 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
7597 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
7598 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
7599 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
7600 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
7601 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
7602 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
7603 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
7604 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
7605 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
7606 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
7607 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
7608 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
7609 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
7870 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, EXT, {RT}},
7871 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, EXT, {RT}},
7880 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, EXT, {RT}},
7881 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, EXT, {RT}},
7890 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, EXT, {RT}},
7891 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, EXT, {RT}},
7892 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, EXT, {RT}},
7893 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, EXT, {RT}},
7894 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, EXT, {RT}},
7895 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, EXT, {RT}},
7896 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, EXT, {RT}},
7897 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, EXT, {RT}},
7898 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, EXT, {RT}},
7899 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, EXT, {RT}},
7900 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, EXT, {RT}},
7901 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, EXT, {RT}},
7902 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, EXT, {RT}},
7909 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, EXT, {RT}},
7910 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, EXT, {RT}},
7912 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, EXT, {RT}},
7913 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, EXT, {RT}},
7915 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, EXT, {RT}},
7916 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, EXT, {RT}},
7918 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, EXT, {RT}},
7920 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, EXT, {RT}},
7922 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, EXT, {RT}},
7925 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, EXT, {RT}},
8050 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
8051 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
8052 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
8053 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
8054 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
8055 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
8056 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
8057 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
8058 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
8059 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
8060 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
8061 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
8062 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
8063 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
8064 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
8065 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
8066 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
8067 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
8068 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
8069 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
8070 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
8071 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
8072 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
8073 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
8074 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
8075 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
8076 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
8077 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
8078 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
8079 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
8080 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
8081 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
8082 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
8083 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
8084 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
8089 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
8307 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, EXT, {RS}},
8308 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, EXT, {RS}},
8317 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, EXT, {RS}},
8318 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, EXT, {RS}},
8327 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, EXT, {RS}},
8328 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, EXT, {RS}},
8329 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, EXT, {RS}},
8330 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, EXT, {RS}},
8331 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, EXT, {RS}},
8332 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, EXT, {RS}},
8333 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, EXT, {RS}},
8334 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, EXT, {RS}},
8335 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, EXT, {RS}},
8336 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, EXT, {RS}},
8337 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, EXT, {RS}},
8338 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, EXT, {RS}},
8339 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, EXT, {RS}},
8346 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, EXT, {RS}},
8347 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, EXT, {RS}},
8349 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, EXT, {RS}},
8350 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, EXT, {RS}},
8352 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, EXT, {RS}},
8353 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, EXT, {RS}},
8355 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, EXT, {RS}},
8357 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, EXT, {RS}},
8359 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, EXT, {RS}},
8361 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, EXT, {RS}},
8373 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
8830 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8831 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8875 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2|EXT, {RT, RA}},
8876 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2|EXT, {RT, RA}},
8877 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8894 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
8906 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
8907 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, EXT, {RT, RA}},
8908 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, EXT, {RT, RA}},
8909 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8926 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},