Lines Matching defs:BB
5352 MachineBasicBlock *BB,
5362 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5390 MachineFunction *MF = BB->getParent();
5391 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5392 MachineFunction::iterator It = BB;
5402 // Transfer the remainder of BB and its successor edges to exitMBB.
5403 exitMBB->splice(exitMBB->begin(), BB,
5405 BB->end());
5406 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5411 BB->addSuccessor(loop1MBB);
5417 BB = loop1MBB;
5418 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5422 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5424 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5426 BB->addSuccessor(loop2MBB);
5427 BB->addSuccessor(exitMBB);
5433 BB = loop2MBB;
5434 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5438 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5440 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5442 BB->addSuccessor(loop1MBB);
5443 BB->addSuccessor(exitMBB);
5447 BB = exitMBB;
5451 return BB;
5455 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5460 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5461 MachineFunction *MF = BB->getParent();
5462 MachineFunction::iterator It = BB;
5471 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5499 // Transfer the remainder of BB and its successor edges to exitMBB.
5500 exitMBB->splice(exitMBB->begin(), BB,
5502 BB->end());
5503 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5514 BB->addSuccessor(loopMBB);
5523 BB = loopMBB;
5524 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5531 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5534 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5538 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5542 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5544 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5547 BB->addSuccessor(loopMBB);
5548 BB->addSuccessor(exitMBB);
5552 BB = exitMBB;
5556 return BB;
5561 MachineBasicBlock *BB,
5567 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5568 MachineFunction *MF = BB->getParent();
5569 MachineFunction::iterator It = BB;
5579 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5610 // Transfer the remainder of BB and its successor edges to exitMBB.
5611 exitMBB->splice(exitMBB->begin(), BB,
5613 BB->end());
5614 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5625 BB->addSuccessor(loopMBB);
5636 BB = loopMBB;
5637 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5645 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5651 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5653 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5656 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5660 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5662 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5665 BB->addSuccessor(loopMBB);
5666 BB->addSuccessor(exitMBB);
5670 BB = exitMBB;
5674 return BB;
5678 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5684 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5685 MachineFunction *MF = BB->getParent();
5686 MachineFunction::iterator It = BB;
5697 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5721 // Transfer the remainder of BB and its successor edges to exitMBB.
5722 exitMBB->splice(exitMBB->begin(), BB,
5724 BB->end());
5725 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5735 BB->addSuccessor(loopMBB);
5752 BB = loopMBB;
5754 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5758 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5759 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5764 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5768 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5770 BB->addSuccessor(exitMBB);
5771 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5772 BB = (i == 0 ? contBB : cont2BB);
5778 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5779 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5782 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5785 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5789 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5790 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5794 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5797 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5799 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5802 BB->addSuccessor(loopMBB);
5803 BB->addSuccessor(exitMBB);
5807 BB = exitMBB;
5811 return BB;
5951 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
5952 ++BB) {
5953 if (!BB->isLandingPad()) continue;
5958 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5968 CallSiteNumToLPad[*CSI].push_back(BB);
6254 MachineBasicBlock *BB = *I;
6258 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6259 BB->succ_end());
6263 BB->removeSuccessor(SMBB);
6268 BB->addSuccessor(DispatchBB);
6275 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6324 llvm_unreachable("Expecting a BB with two successors!");
6328 EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const {
6333 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6334 MachineFunction::iterator It = BB;
6344 MachineFunction *MF = BB->getParent();
6400 AddDefaultPred(BuildMI(*BB, MI, dl,
6404 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6407 AddDefaultPred(BuildMI(*BB, MI, dl,
6411 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6415 AddDefaultPred(BuildMI(*BB, MI, dl,
6420 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6438 AddDefaultPred(BuildMI(*BB, MI, dl,
6442 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6446 AddDefaultPred(BuildMI(*BB, MI, dl,
6451 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6459 return BB;
6487 // Transfer the remainder of BB and its successor edges to exitMBB.
6488 exitMBB->splice(exitMBB->begin(), BB,
6490 BB->end());
6491 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6499 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
6503 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
6517 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
6522 BB->addSuccessor(loopMBB);
6528 MachineBasicBlock *entryBB = BB;
6529 BB = loopMBB;
6537 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
6540 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
6543 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
6551 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6554 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6557 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6560 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6564 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6568 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6574 MachineInstrBuilder MIB = BuildMI(BB, dl,
6580 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6584 BB->addSuccessor(loopMBB);
6585 BB->addSuccessor(exitMBB);
6588 BB = exitMBB;
6602 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
6606 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
6610 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
6614 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
6623 return BB;
6628 MachineBasicBlock *BB) const {
6642 return BB;
6645 return BB;
6648 return BB;
6662 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6671 return BB;
6683 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
6687 return BB;
6690 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6692 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6694 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6697 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6699 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6701 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6704 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6706 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6708 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6711 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6713 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6715 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6718 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6720 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6722 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6725 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6727 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6729 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6732 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
6734 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
6736 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
6739 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
6741 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
6743 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
6746 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
6748 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
6750 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
6753 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
6755 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
6757 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
6759 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
6760 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
6761 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
6763 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
6764 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
6765 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
6769 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
6773 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6777 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
6780 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
6783 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
6786 return EmitAtomicBinary64(MI, BB, 0, 0, false);
6788 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6797 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6798 MachineFunction::iterator It = BB;
6807 MachineBasicBlock *thisMBB = BB;
6808 MachineFunction *F = BB->getParent();
6814 // Transfer the remainder of BB and its successor edges to sinkMBB.
6815 sinkMBB->splice(sinkMBB->begin(), BB,
6817 BB->end());
6818 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6820 BB->addSuccessor(copy0MBB);
6821 BB->addSuccessor(sinkMBB);
6823 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
6829 BB = copy0MBB;
6832 BB->addSuccessor(sinkMBB);
6837 BB = sinkMBB;
6838 BuildMI(*BB, BB->begin(), dl,
6844 return BB;
6850 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
6859 AddDefaultPred(BuildMI(BB, dl,
6862 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6868 AddDefaultPred(BuildMI(BB, dl,
6871 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6877 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
6881 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6884 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6886 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6889 return BB;
6897 EmitSjLjDispatchBlock(MI, BB);
6898 return BB;
6914 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6915 MachineFunction::iterator BBI = BB;
6917 MachineFunction *Fn = BB->getParent();
6933 // Transfer the remainder of BB and its successor edges to sinkMBB.
6934 SinkBB->splice(SinkBB->begin(), BB,
6936 BB->end());
6937 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6939 BB->addSuccessor(RSBBB);
6940 BB->addSuccessor(SinkBB);
6945 // insert a cmp at the end of BB
6946 AddDefaultPred(BuildMI(BB, dl,
6950 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6951 BuildMI(BB, dl,
6968 .addReg(ABSSrcReg).addMBB(BB);
6973 // return last added BB
6978 return EmitStructByval(MI, BB);