Lines Matching refs:on
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
37 * ml_set_physical() -- turn off DR and (if 64-bit) turn SF on
39 * ml_set_physical_get_ffs() -- turn DR off, SF on, and get feature flags
40 * ml_set_physical_disabled() -- turn DR and EE off, SF on, get feature flags
41 * ml_set_translation_off() -- turn DR, IR, and EE off, SF on, get feature flags
153 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
169 beq- mprdoit ; We are right on the boundary...
198 rlwinm r5, r6, 0, mum+1, mum-1 ; Turn off MuM w/ I-Cache on
228 ori r11,r2,lo16(MASK(MSR_DR)) ; Turn on data translation
292 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
298 mpr64bit: andi. r0,r3,3 ; Check if we are on a word boundary
305 or r12,r10,r11 ; Turn on EE if on before we turned it off
313 mtmsrd r10 ; Translation and EE off, 64-bit on
388 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
419 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
456 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
487 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
518 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
548 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
584 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
615 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
703 andi. r4,r3,1 ; Are we turning interruptions on?
709 bne CheckPreemption ; Interrupts going on, check ASTs...
720 ori r5,r5,lo16(MASK(MSR_EE)) ; Turn on the enable
877 nonap: ori r3,r3,lo16(MASK(MSR_EE)) ; Flip on EE
879 mtmsr r3 ; Turn interruptions back on
920 ; turn on only the POW bit and that we should have interrupts enabled.
936 ori r7,r5,lo16(MASK(MSR_EE)) ; Flip on EE to make exit msr
939 ori r5,r5,lo16(MASK(MSR_EE)) ; Flip on EE to make nap msr
940 oris r2,r5,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
958 mtmsr r5 ; Turn translation off, interrupts on
980 mtmsr r6 ; Set MSR with EE off but POW on
1005 isync ; In case we turn on translation
1071 bt++ pf64Bitb,mpsPF64bit ; PM bits are shifted on 64bit systems.
1117 ori r3,r5,lo16(MASK(MSR_EE)) ; Flip on EE
1141 bl EXT(cacheInit) ; Clear out the caches. This will leave them on
1145 oris r5,r5,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
1180 * check if the cache is on, if so, we need to flush the contents to memory.
1182 * Finally we turn on all of the caches
1274 rlwinm. r0,r9,0,ice,dce ; Were either of the level 1s on?
1281 oris r8,r8,hi16(dl1hwfm) ; Turn on the hardware flush request
1367 b cinoL1 ; Go on to level 2...
1392 mtspr hid0,r8 ; Start the invalidate and turn on cache
1461 b ciswfl2doc ; Jump back up and turn on data only...
1613 ; Invalidate and turn on L1s
1628 mtspr hid0,r8 ; Start the invalidate and turn on L1 cache
1669 or r3,r3,r11 ; Turn on the flash invalidate L1D$
1736 beq++ cflushx ; Keep on flushing...
1792 * Turns off all caches on the processor. They are not flushed.
2049 stwu r1, -(FM_ALIGN(4*4)+FM_SIZE)(r1) ; Make some space on the stack
2110 mtspr hid0, r28 ; Turn on dnap in hid0 if needed
2286 or r12,r10,r11 ; Turn on EE if on before we turned it off
2298 mtmsrd r12,1 ; Flip EE on if needed