Lines Matching refs:mtspr
196 mtspr hid0, r5
199 mtspr hid0, r5
321 mtspr hid4,r2 ; Make real accesses cache-inhibited
340 mtspr hid4,r8 ; Make real accesses not cache-inhibited
648 mtspr hid4,r2 ; Make real accesses cache-inhibited
678 mtspr hid4,r8 ; Make real accesses not cache-inhibited
905 mtspr msscr0,r7 ; Updates MSSCR0 value
915 mtspr hid1,r7 ; Update HID1 value
943 mtspr hid0,r6 ; Set up the HID for nap/doze
1066 mtspr msscr0,r5 ; Updates MSSCR0 value
1119 mtspr hid0,r4 ; Set up the HID to sleep
1212 mtspr hid0,r4 ; Set up the HID
1283 mtspr msscr0,r8 ; Start the flush operation
1308 mtspr msscr0,r6 ; Set it
1331 mtspr ldstcr,r5 ; Lock a way
1359 mtspr ldstcr,r8 ; Slam back to original
1363 mtspr msscr0,r4 ; ?
1384 mtspr hid0,r8 ; and turn off L1 cache
1392 mtspr hid0,r8 ; Start the invalidate and turn on cache
1394 mtspr hid0,r8 ; Turn off the invalidate (needed for some older machines)
1428 mtspr l2cr,r10 ; Lock out the cache
1435 mtspr l2cr,r10 ; Request flush
1450 mtspr l2cr,r2 ; Disable L2
1475 cinlc: mtspr l2cr,r8 ; Disable L2
1494 mtspr l2cr,r2 ; Start the invalidate
1509 mtspr l2cr,r8 ; Turn off the invalidate request
1539 mtspr l3cr,r10 ; Lock out the cache
1546 mtspr l3cr,r10 ; Request flush
1554 mtspr l3cr,r8 ; Disable L3
1562 mtspr l3cr,r8 ; Start the invalidate
1581 mtspr l3pdet, r8 ; ?
1587 mtspr l3cr,r8 ; Disable the clock
1596 mtspr msssr0,r10 ; ?
1599 mtspr l3cr,r3 ; Enable it as desired
1609 mtspr l2cr,r3 ; Enable it as desired
1620 mtspr hid0,r8 ; Turn off dem caches
1628 mtspr hid0,r8 ; Start the invalidate and turn on L1 cache
1630 cinoexit: mtspr hid0,r9 ; Turn off the invalidate (needed for some older machines) and restore entry conditions
1657 mtspr hid1,r10 ; Stick it
1658 mtspr hid1,r10 ; Stick it again
1664 mtspr hid4,r11 ; Stick it
1673 mtspr hid4,r3 ; Invalidate
1676 mtspr hid4,r5 ; Un-invalidate and disable L1D$
1686 mtspr scomc,r8 ; Request the GUS mode
1699 mtspr scomd,r6 ; Set that we want direct L2 mode
1700 mtspr scomc,r8 ; Tell GUS we want direct L2 mode
1743 mtspr hid1,r3 ; Stick it
1744 mtspr hid1,r3 ; Stick it again
1756 mtspr scomd,r11 ; Set that we do not want direct mode
1757 mtspr scomc,r8 ; Tell GUS we do not want direct mode
1763 mtspr hid0,r9 ; Restore entry hid0
1773 mtspr hid1,r12 ; Restore entry hid1
1774 mtspr hid1,r12 ; Stick it again
1778 mtspr hid4,r4 ; Restore entry hid4
1815 mtspr hid0,r5 ; Turn off dem caches
1827 cinlcc: mtspr l2cr,r5 ; Disable L2
1845 mtspr l3cr,r5 ; Disable the caches
2073 mtspr hid0, r3 ; Turn off dnap in hid0
2110 mtspr hid0, r28 ; Turn on dnap in hid0 if needed
2145 mtspr hid0, r4 ; Set the new hid0 value
2153 mtspr hid1, r4 ; Select desired PLL
2159 mtspr hid0, r4 ; Set the hid0 value
2185 mtspr hid1,r4 ; Set the new HID1
2210 mtspr hid2, r4 ; Set the voltage mode
2232 mtspr scomd,r5 ; Stick in the data
2233 mtspr scomc,r3 ; Set write to register
2259 mtspr scomc,r3 ; Request the register