Lines Matching refs:bit
37 * ml_set_physical() -- turn off DR and (if 64-bit) turn SF on
63 bt++ pf64Bitb,ml_set_physical_64 // skip if 64-bit (only they take the hint)
95 ori r0,r0,lo16(MASK(MSR_DR)+MASK(MSR_FP)) // always turn off DR and FP bit
97 bt++ pf64Bitb,ml_set_physical_64 // skip if 64-bit (only they take the hint)
105 rldimi r2,r0,63,MSR_SF_BIT // set SF bit (bit 0)
106 mtmsrd r2 // set 64-bit mode, turn off data relocation
124 bt++ pf64Bitb,ml_restore_64 // handle 64-bit cpus (only they take the hint)
125 mtmsr r11 // restore a 32-bit MSR
130 mtmsrd r11 // restore a 64-bit MSR
153 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
154 rlwinm r3,r3,0,0,31 ; Clean up for 64-bit machines
155 bne++ mpr64bit ; Go do this the 64-bit way...
274 /* PCI config cycle probing - 64-bit
292 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
293 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
296 beq-- mpr32bit ; Go do this the 32-bit way...
299 li r0,0 ; Clear the EE bit (and everything else for that matter)
302 mtmsrd r0,1 ; Set the EE bit only (do not care about RI)
303 rlwinm r11,r11,0,MSR_EE_BIT,MSR_EE_BIT ; Isolate just the EE bit
308 sldi r2,r2,63 ; Get the 64-bit bit
310 or r10,r10,r2 ; Set 64-bit
313 mtmsrd r10 ; Translation and EE off, 64-bit on
316 sldi r0,r0,32+8 ; Get the right bit to inhibit caching
319 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
379 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
388 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
410 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
419 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
445 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
456 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
478 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
487 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
508 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
518 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
538 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
548 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
572 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
584 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
604 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
615 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
631 li r2,1 ; Prepare for 64 bit
633 bf-- pf64Bitb,rdwrpre32 ; Join 32-bit code...
636 rldimi r9,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
638 mtmsrd r9 ; set 64-bit mode, turn off EE, DR, and IR
641 sldi r0,r2,32+8 ; Get the right bit to turn off caching
646 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
661 rdwrpre32: rlwimi r9,r10,0,MSR_IR_BIT,MSR_IR_BIT ; Leave the IR bit unchanged
669 bt++ pf64Bitb,rdwrpost64 ; Join 64-bit code...
694 * Set EE bit to "enable" and return old value as boolean
920 ; turn on only the POW bit and that we should have interrupts enabled.
929 bf-- pf64Bitb,mipNSF1 ; skip if 32-bit...
966 miNoMSRx: bf-- pf64Bitb,mipowloop ; skip if 32-bit...
978 rlwinm r6,r2,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Clear out the EE bit
1026 * There is one bit of hackery in here: we need to enable for
1071 bt++ pf64Bitb,mpsPF64bit ; PM bits are shifted on 64bit systems.
1092 li r2,1 ; Prepare for 64 bit
1098 bf++ pf64Bitb,mpsCheckMSR ; check 64-bit processor
1099 rldimi r5,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
1100 mtmsrd r5 ; set 64-bit mode, turn off EE, DR, and IR
1130 add r6,r6,r4 ; A bit more
1131 add r6,r6,r5 ; A bit more
1155 rlwinm. r0,r11,0,pf64Bitb,pf64Bitb ; Test for 64 bit processor
1158 beq slSleepNow ; skip if 32-bit...
1207 bf-- pf64Bitb,cIniNSF1 ; Skip if 32-bit...
1241 bf-- pf64Bitb,citlbhang ; Skip if 32-bit...
1266 bf-- pf64Bitb,cinoSMP ; Skip if 32-bit...
1272 bt++ pf64Bitb,cin64 ; Skip if 64-bit...
1471 ciinvdl2: rlwinm r8,r3,0,l2e+1,31 ; Clear the enable bit
1552 ciinvdl3: rlwinm r8,r3,0,l3e+1,31 ; Clear the enable bit
1586 rlwinm r8,r8,0,l3clken+1,l3clken-1 ; Clear the clock enable bit
1638 ; Handle 64-bit architecture
1667 li r3,8 ; Set bit 28+32
1668 sldi r3,r3,32 ; Make it bit 28
1694 ori r6,r11,lo16(GUSMdmapen) ; Set the bit that means direct L2 cache address
1710 addis r6,r6,8 ; Roll bit 42:44
1712 addis r6,r6,8 ; Roll bit 42:44
1714 addis r6,r6,8 ; Roll bit 42:44
1716 addis r6,r6,8 ; Roll bit 42:44
1718 addis r6,r6,8 ; Roll bit 42:44
1720 addis r6,r6,8 ; Roll bit 42:44
1722 addis r6,r6,8 ; Roll bit 42:44
1811 btlr pf64Bitb ; No way to disable a 64-bit machine...
1822 rlwinm r5,r5,0,l2e+1,31 ; Turn off enable bit
1843 rlwinm r5,r5,0,l3e+1,31 ; Turn off enable bit
1844 rlwinm r5,r5,0,l3clken+1,l3clken-1 ; Turn off cache enable bit
1912 ** Entry - R3 contains pointer to 64 bit structure.
1914 ** Exit - 64 bit structure filled in.
2059 rlwinm r28, r3, 31-dnap, dnap, dnap ; Shift the 1 bit to the dnap+32 bit
2066 and r28, r28, r3 ; Save the dnap bit
2067 lis r4, hi16(dnapm) ; Make a mask for the dnap bit
2069 andc r3, r3, r4 ; Clear the dnap bit
2070 or r28, r28, r3 ; Insert the dnap bit as needed for later
2102 rlwimi r0, r5, 0, 2, 2 ; Copy in the change in progress bit
2143 rlwinm r4, r4, 0, btic+1, btic-1 ; Clear the BTIC bit
2151 rlwimi r4, r3, 31-hid1ps, hid1ps, hid1ps ; Copy the PLL Select bit
2209 rlwimi r4, r3, 31-hid2vmin, hid2vmin, hid2vmin ; Insert the voltage mode bit
2219 ; 64-bit machines only
2242 ; 64-bit machines only
2244 ; ASM Callers: data (r4) can be zero and the 64 bit data will be returned in r5
2281 li r0,0 ; Clear the EE bit (and everything else for that matter)
2283 mtmsrd r0,1 ; Set the EE bit only (do not care about RI)
2284 rlwinm r11,r11,0,MSR_EE_BIT,MSR_EE_BIT ; Isolate just the EE bit