Lines Matching refs:L2
900 minovec: rlwinm. r7,r11,0,pfNoL2PFNapb,pfNoL2PFNapb ; Turn off L2 Prefetch before nap?
904 rlwinm r7,r7,0,0,l2pfes-1 ; Disable L2 Prefetch
1061 rlwinm. r5,r11,0,pfNoL2PFNapb,pfNoL2PFNapb ; Turn off L2 Prefetch before sleep?
1065 rlwinm r5,r5,0,0,l2pfes-1 ; Disable L2 Prefetch
1181 * Then we invalidate the L1. Next, we configure and invalidate the L2 etc.
1403 rlwinm. r0,r10,0,pfL2b,pfL2b ; do we have L2?
1408 rlwinm. r0,r8,0,l2e,l2e ; Was the L2 enabled?
1410 cmplwi r8, 0 ; Was the L2 all the way off?
1419 rlwinm. r0,r10,0,pfL2fab,pfL2fab ; hardware-assisted L2 flush?
1440 b ciinvdl2 ; Flush done, go invalidate L2...
1443 lwz r0,pfl2Size(r12) ; Get the L2 size
1444 oris r2,r8,hi16(l2dom) ; Set L2 to data only mode
1450 mtspr l2cr,r2 ; Disable L2
1475 cinlc: mtspr l2cr,r8 ; Disable L2
1489 cmplwi r3, 0 ; Should the L2 be all the way off?
1490 beq cinol2 ; Yes, done with L2
1603 rlwinm. r0,r0,0,pfL2b,pfL2b ; is there an L2 cache?
1607 cmplwi r3, 0 ; Should the L2 be all the way off?
1608 beq cinol2a : Yes, done with L2
1694 ori r6,r11,lo16(GUSMdmapen) ; Set the bit that means direct L2 cache address
1699 mtspr scomd,r6 ; Set that we want direct L2 mode
1700 mtspr scomc,r8 ; Tell GUS we want direct L2 mode
1818 rlwinm. r0,r11,0,pfL2b,pfL2b ; is there an L2?
1819 beq cdNoL2 ; Skip if no L2...
1821 mfspr r5,l2cr ; Get the L2
1827 cinlcc: mtspr l2cr,r5 ; Disable L2