Lines Matching refs:r7
200 li r7,1 ; Get set for it
204 rldimi r8,r7,63,MSR_SF_BIT ; Set SF bit (bit 0)
219 lwz r7,8(r3) /* Get word 2 */
240 stw r7,8(r4) /* Set word 2 */
275 lwz r7,12(r3) /* Get DBAT 1 low */
285 mtdbatl 1,r7 /* Load DBAT 1 low */
318 lwz r7,12(r3) /* Get IBAT 1 low */
328 mtibatl 1,r7 /* Load IBAT 1 low */
355 mr r6,r7
453 li r7,0x09 /* Set the register */
454 stb r7,0(r10) /* Set the register */
460 li r7,0x80 /* Reset channel A */
461 stb r7,0(r10) /* Set the register */
467 li r7,0x04 /* Set the register */
468 stb r7,0(r10) /* Set the register */
474 li r7,0x44 /* x16 clock, 1 stop bit */
475 stb r7,0(r10) /* Set the register */
481 li r7,0x03 /* Set the register */
482 stb r7,0(r10) /* Set the register */
488 li r7,0xC0 /* 8 bits per char */
489 stb r7,0(r10) /* Set the register */
495 li r7,0x05 /* Set the register */
496 stb r7,0(r10) /* Set the register */
502 li r7,0xE2 /* DTR mode, 8bit/char */
503 stb r7,0(r10) /* Set the register */
509 li r7,0x02 /* Set the register */
510 stb r7,0(r10) /* Set the register */
516 li r7,0x00 /* Vector 0 */
517 stb r7,0(r10) /* Set the register */
523 li r7,0x0A /* Set the register */
524 stb r7,0(r10) /* Set the register */
530 li r7,0x00 /* Clear misc controls */
531 stb r7,0(r10) /* Set the register */
537 li r7,0x0B /* Set the register */
538 stb r7,0(r10) /* Set the register */
544 li r7,0x50 /* B/R gen T/R */
545 stb r7,0(r10) /* Set the register */
551 li r7,0x0C /* Set the register */
552 stb r7,0(r10) /* Set the register */
558 li r7,0x0A /* 9600 baud low */
559 stb r7,0(r10) /* Set the register */
565 li r7,0x0D /* Set the register */
566 stb r7,0(r10) /* Set the register */
572 li r7,0x00 /* 9600 baud high */
573 stb r7,0(r10) /* Set the register */
579 li r7,0x03 /* Set the register */
580 stb r7,0(r10) /* Set the register */
586 li r7,0xC1 /* 8 bits/char, Rx enable */
587 stb r7,0(r10) /* Set the register */
593 li r7,0x05 /* Set the register */
594 stb r7,0(r10) /* Set the register */
600 li r7,0xEA /* 8 bits/char, Tx enable */
601 stb r7,0(r10) /* Set the register */
607 li r7,0x0E /* Set the register */
608 stb r7,0(r10) /* Set the register */
614 li r7,0x01 /* BR rate gen enable */
615 stb r7,0(r10) /* Set the register */
621 li r7,0x0F /* Set the register */
622 stb r7,0(r10) /* Set the register */
628 li r7,0x00 /* ints off */
629 stb r7,0(r10) /* Set the register */
635 li r7,0x10 /* Reset ext/stat ints */
636 stb r7,0(r10) /* Set the register */
642 li r7,0x10 /* Reset ext/stat ints */
643 stb r7,0(r10) /* Set the register */
649 li r7,0x01 /* Set the register */
650 stb r7,0(r10) /* Set the register */
656 li r7,0x10 /* int on Rx, no Tx int enable */
657 stb r7,0(r10) /* Set the register */
663 li r7,0x09 /* Set the register */
664 stb r7,0(r10) /* Set the register */
670 li r7,0x0A /* int on Rx, Tx int enable */
671 stb r7,0(r10) /* Set the register */
677 li r7,0x09 /* Set the register */
678 stb r7,0(r10) /* Set the register */
684 li r7,0x02 /* No vector */
685 stb r7,0(r10) /* Set the register */
691 lbz r7,0(r10) /* Clear interrupts */
697 lbz r7,0(r10) /* Get current status */
700 andi. r7,r7,0x04 /* Is transmitter empty? */
746 li r7,0x35 /* (TEST/DEBUG) */
747 stb r7,4(r10) /* (TEST/DEBUG) */
749 lis r7,10 /* (TEST/DEBUG) */
750 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
751 mr. r7,r7 /* (TEST/DEBUG) */
765 mr r7,r12 /* (TEST/DEBUG) */
793 lbz r7,0(r12) /* (TEST/DEBUG) */
796 andi. r7,r7,0x04 /* (TEST/DEBUG) */
800 li r7,0x36 /* (TEST/DEBUG) */
801 stb r7,4(r12) /* (TEST/DEBUG) */
809 lis r7,10 /* (TEST/DEBUG) */
810 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
811 mr. r7,r7 /* (TEST/DEBUG) */
836 lis r7,0xF300 /* Address of SCC rounded to 128k */
837 ori r7,r7,0x0032 /* Make it cache inhibited */
838 mtdbatl 3,r7 /* Load DBAT 3 low */
839 lis r7,0xF300 /* Address of SCC rounded to 128k */
840 ori r7,r7,0x0002 /* Make it supervisor only */
841 mtdbatu 3,r7 /* Load DBAT 3 high */
851 mr r7,r10 /* (TEST/DEBUG) */
865 li r7,0x37 /* (TEST/DEBUG) */
866 stb r7,4(r12) /* (TEST/DEBUG) */
868 lis r7,12 /* (TEST/DEBUG) */
869 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
870 mr. r7,r7 /* (TEST/DEBUG) */
884 lwarx r7,0,r12 ; ?
886 ddwait0: lwarx r7,0,r12 /* Get the lock */
887 mr. r7,r7 /* Is it locked? */
897 li r7,0x38 /* (TEST/DEBUG) */
898 stb r7,6(r10) /* (TEST/DEBUG) */
900 lis r7,10 /* (TEST/DEBUG) */
901 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
902 mr. r7,r7 /* (TEST/DEBUG) */
930 li r7,0 /* Get a zero */
931 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
932 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
935 li r7,0 /* Get a zero */
938 stw r7,0(r12) /* Release the display lock */
971 lis r7,3 /* Get enough for about 1ms */
973 dbgDchar0: addi r7,r7,-1 /* Count down */
974 mr. r7,r7 /* Waited long enough? */
979 li r7,0x01 /* ? */
980 stb r7,0(r10) /* ? */
986 lbz r7,0(r10) /* ? */
991 li r7,0x00 /* ? */
992 stb r7,0(r10) /* ? */
998 lbz r7,0(r10) /* ? */
1005 lbz r7,0(r10) /* ? */
1008 andi. r7,r7,0x04 /* ? */
1020 lbz r7,0(r10) /* ? */
1023 andi. r7,r7,0x04 /* ? */
1028 li r7,0x10 /* ? */
1029 stb r7,0(r10) /* ? */
1035 lbz r7,0(r10) /* ? */
1041 lis r7,0x0080 /* ? */
1043 ori r7,r7,0x010F /* ? */
1044 stw r7,0x28(r9) /* ? */
1055 li r7,0x03 /* ? */
1056 stb r7,0(r9) /* ? */
1059 lbz r7,0(r9) /* ? */
1062 lbz r7,0(r9) /* ? */
1065 lbz r7,0(r10) /* ? */
1066 andi. r7,r7,0x04 /* ? */
1074 lbz r7,0(r10) /* ? */
1075 andi. r7,r7,0x04 /* ? */
1079 lbz r7,0(r10) /* ? */
1080 andi. r7,r7,0x40 /* ? */
1084 li r7,0xC0 /* ? */
1085 stb r7,0(r10) /* ? */
1088 li r7,0x10 /* ? */
1089 stb r7,0(r10) /* ? */
1092 li r7,0x38 /* ? */
1093 stb r7,0(r9) /* ? */
1096 li r7,0x30 /* ? */
1097 stb r7,0(r10) /* ? */
1100 li r7,0x20 /* ? */
1101 stb r7,0(r10) /* ? */
1158 lis r7,0xF300 /* ? */
1159 ori r7,r7,0x0032 /* ? */
1160 mtdbatl 3,r7 /* ? */
1161 lis r7,0xF300 /* ? */
1162 ori r7,r7,0x0002 /* ? */
1163 mtdbatu 3,r7 /* ? */
1507 li r7,0 /* Get a zero */
1508 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1509 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1512 li r7,0 /* Get a zero */
1514 stw r7,0(r3) /* Clear display lock */
1557 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1568 stw r7,0x0C(r12) /* Store it */
1580 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1592 stw r7,0x0C(r12) /* Store it */
1604 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1616 stw r7,0x0C(r12) /* Store it */
1628 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1637 stw r7,0x0C(r12) /* Store it */
1852 li r7,32 /* Number of bits per word */
1871 sub. r7,r7,r26 /* See how may bits are left */
1878 li r7,32 /* Bit per word count */
1946 mflr r7 /* Save the return */
1952 mtlr r7 /* Restore return */
1973 lis r7,0xF300 /* Find it */
1975 ori r7,r7,0x0020 /* Find it */
1977 dcbi 0,r7 /* Toss it */
1981 lwz r6,0x000C(r7) /* Check it */
1983 dcbi 0,r7 /* Toss it */
1990 stw r6,0x0008(r7) /* Reset it */
2206 mfdbatl r7,1
2214 stw r7,20(r3)
2223 mfibatl r7,1
2231 stw r7,52(r3)
2240 mfsprg r7,3
2244 stw r7,84(r3)
2266 li r7,0
2271 mfspr r7,msscr1
2276 stw r7,(43*4)(r3)
2287 li r7,0
2293 mfspr r7,ictc
2298 stw r7,(47*4)(r3)
2326 mfsprg r7,3
2330 std r7,(24*4)(r3)
2349 slbmfev r7,r5
2351 std r7,8(r4)
2377 rlwinm r7,r7,0,1,0 ; Copy low of high high - hid4
2380 rlwimi r7,r8,0,0,31 ; Copy low of low low
2393 and r7,r7,r10 ; Keep only error inject controls - hid4
2399 or r2,r2,r7 ; Add in the new controls hid4