Lines Matching defs:mcbsp
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
23 #include "omap-mcbsp-priv.h"
24 #include "omap-mcbsp.h"
38 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
40 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
41 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
42 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
43 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
44 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
45 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
46 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
47 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
48 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
49 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
50 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
51 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
52 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
53 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
54 dev_dbg(mcbsp->dev, "***********************\n");
57 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
70 fck_src = clk_get(mcbsp->dev, src);
72 dev_info(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
76 if (mcbsp->active)
77 pm_runtime_put_sync(mcbsp->dev);
79 r = clk_set_parent(mcbsp->fclk, fck_src);
81 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
84 if (mcbsp->active)
85 pm_runtime_get_sync(mcbsp->dev);
94 struct omap_mcbsp *mcbsp = data;
97 irqst = MCBSP_READ(mcbsp, IRQST);
98 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
101 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
103 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
105 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
107 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
109 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
111 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
114 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
116 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
118 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
120 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
122 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
124 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
126 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
128 MCBSP_WRITE(mcbsp, IRQST, irqst);
135 struct omap_mcbsp *mcbsp = data;
138 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
139 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
142 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
145 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
153 struct omap_mcbsp *mcbsp = data;
156 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
157 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
160 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
163 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
175 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
178 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
179 mcbsp->id, mcbsp->phys_base);
182 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
183 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
184 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
185 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
186 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
187 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
188 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
189 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
190 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
191 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
192 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
193 if (mcbsp->pdata->has_ccr) {
194 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
195 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
198 if (mcbsp->pdata->has_wakeup)
199 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
202 if (mcbsp->irq)
203 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
208 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
209 * @mcbsp: omap_mcbsp struct for the McBSP instance
212 * Returns the address of mcbsp data transmit register or data receive register
215 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
221 if (mcbsp->pdata->reg_size == 2)
226 if (mcbsp->pdata->reg_size == 2)
232 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
240 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
242 if (threshold && threshold <= mcbsp->max_tx_thres)
243 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
251 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
253 if (threshold && threshold <= mcbsp->max_rx_thres)
254 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
260 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
265 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
268 return mcbsp->pdata->buffer_size - buffstat;
275 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
280 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
282 threshold = MCBSP_READ(mcbsp, THRSH1);
291 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
296 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
300 spin_lock(&mcbsp->lock);
301 if (!mcbsp->free) {
302 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
307 mcbsp->free = false;
308 mcbsp->reg_cache = reg_cache;
309 spin_unlock(&mcbsp->lock);
311 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
312 mcbsp->pdata->ops->request(mcbsp->id - 1);
318 MCBSP_WRITE(mcbsp, SPCR1, 0);
319 MCBSP_WRITE(mcbsp, SPCR2, 0);
321 if (mcbsp->irq) {
322 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
323 "McBSP", (void *)mcbsp);
325 dev_err(mcbsp->dev, "Unable to request IRQ\n");
329 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
330 "McBSP TX", (void *)mcbsp);
332 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
336 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
337 "McBSP RX", (void *)mcbsp);
339 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
346 free_irq(mcbsp->tx_irq, (void *)mcbsp);
348 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
349 mcbsp->pdata->ops->free(mcbsp->id - 1);
352 if (mcbsp->pdata->has_wakeup)
353 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
355 spin_lock(&mcbsp->lock);
356 mcbsp->free = true;
357 mcbsp->reg_cache = NULL;
359 spin_unlock(&mcbsp->lock);
365 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
369 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
370 mcbsp->pdata->ops->free(mcbsp->id - 1);
373 if (mcbsp->pdata->has_wakeup)
374 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
377 if (mcbsp->irq) {
378 MCBSP_WRITE(mcbsp, IRQEN, 0);
380 free_irq(mcbsp->irq, (void *)mcbsp);
382 free_irq(mcbsp->rx_irq, (void *)mcbsp);
383 free_irq(mcbsp->tx_irq, (void *)mcbsp);
386 reg_cache = mcbsp->reg_cache;
396 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
398 spin_lock(&mcbsp->lock);
399 if (mcbsp->free)
400 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
402 mcbsp->free = true;
403 mcbsp->reg_cache = NULL;
404 spin_unlock(&mcbsp->lock);
414 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
421 if (mcbsp->st_data)
422 omap_mcbsp_st_start(mcbsp);
425 w = MCBSP_READ_CACHE(mcbsp, PCR0);
427 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
428 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
432 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
433 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
438 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
439 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
442 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
443 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
455 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
456 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
459 if (mcbsp->pdata->has_ccr) {
461 w = MCBSP_READ_CACHE(mcbsp, XCCR);
463 MCBSP_WRITE(mcbsp, XCCR, w);
464 w = MCBSP_READ_CACHE(mcbsp, RCCR);
466 MCBSP_WRITE(mcbsp, RCCR, w);
470 omap_mcbsp_dump_reg(mcbsp);
473 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
482 if (mcbsp->pdata->has_ccr) {
483 w = MCBSP_READ_CACHE(mcbsp, XCCR);
485 MCBSP_WRITE(mcbsp, XCCR, w);
487 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
488 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
492 if (mcbsp->pdata->has_ccr) {
493 w = MCBSP_READ_CACHE(mcbsp, RCCR);
495 MCBSP_WRITE(mcbsp, RCCR, w);
497 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
498 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
500 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
501 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
505 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
506 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
509 if (mcbsp->st_data)
510 omap_mcbsp_st_stop(mcbsp);
513 #define max_thres(m) (mcbsp->pdata->buffer_size)
519 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
521 return sysfs_emit(buf, "%u\n", mcbsp->prop); \
528 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
536 if (!valid_threshold(mcbsp, val)) \
539 mcbsp->prop = val; \
555 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
560 dma_op_mode = mcbsp->dma_op_mode;
577 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
584 spin_lock_irq(&mcbsp->lock);
585 if (!mcbsp->free) {
589 mcbsp->dma_op_mode = i;
592 spin_unlock_irq(&mcbsp->lock);
616 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
620 spin_lock_init(&mcbsp->lock);
621 mcbsp->free = true;
627 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
628 if (IS_ERR(mcbsp->io_base))
629 return PTR_ERR(mcbsp->io_base);
631 mcbsp->phys_base = res->start;
632 mcbsp->reg_cache_size = resource_size(res);
636 mcbsp->phys_dma_base = mcbsp->phys_base;
638 mcbsp->phys_dma_base = res->start;
647 mcbsp->irq = platform_get_irq_byname(pdev, "common");
648 if (mcbsp->irq == -ENXIO) {
649 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
651 if (mcbsp->tx_irq == -ENXIO) {
652 mcbsp->irq = platform_get_irq(pdev, 0);
653 mcbsp->tx_irq = 0;
655 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
656 mcbsp->irq = 0;
666 mcbsp->dma_req[0] = res->start;
667 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
674 mcbsp->dma_req[1] = res->start;
675 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
677 mcbsp->dma_data[0].filter_data = "tx";
678 mcbsp->dma_data[1].filter_data = "rx";
681 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
683 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
686 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
687 if (IS_ERR(mcbsp->fclk)) {
688 ret = PTR_ERR(mcbsp->fclk);
689 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
693 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
694 if (mcbsp->pdata->buffer_size) {
703 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
704 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
706 ret = devm_device_add_group(mcbsp->dev, &additional_attr_group);
708 dev_err(mcbsp->dev,
726 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
730 if (mcbsp->pdata->buffer_size == 0)
746 omap_mcbsp_set_tx_threshold(mcbsp, words);
748 omap_mcbsp_set_rx_threshold(mcbsp, words);
758 struct omap_mcbsp *mcbsp = rule->private;
763 size = mcbsp->pdata->buffer_size;
773 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
777 err = omap_mcbsp_request(mcbsp);
794 if (mcbsp->pdata->buffer_size) {
804 mcbsp,
818 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
823 if (mcbsp->latency[stream2])
824 cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
825 mcbsp->latency[stream2]);
826 else if (mcbsp->latency[stream1])
827 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
829 mcbsp->latency[stream1] = 0;
832 omap_mcbsp_free(mcbsp);
833 mcbsp->configured = 0;
840 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
841 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
845 int latency = mcbsp->latency[stream2];
848 if (!latency || mcbsp->latency[stream1] < latency)
849 latency = mcbsp->latency[stream1];
862 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
868 mcbsp->active++;
869 omap_mcbsp_start(mcbsp, substream->stream);
875 omap_mcbsp_stop(mcbsp, substream->stream);
876 mcbsp->active--;
891 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
896 if (mcbsp->pdata->buffer_size == 0)
900 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
902 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
918 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
919 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
924 unsigned int buffer_size = mcbsp->pdata->buffer_size;
942 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
948 max_thrsh = mcbsp->max_tx_thres;
950 max_thrsh = mcbsp->max_rx_thres;
976 mcbsp->latency[substream->stream] = latency;
983 if (mcbsp->configured) {
992 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1030 master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
1032 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1033 framesize = (mcbsp->in_freq / div) / params_rate(params);
1059 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1060 mcbsp->wlen = wlen;
1061 mcbsp->configured = 1;
1073 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1074 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1077 if (mcbsp->configured)
1080 mcbsp->fmt = fmt;
1086 if (!mcbsp->pdata->has_ccr) {
1092 if (mcbsp->pdata->has_ccr) {
1182 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1183 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1188 mcbsp->clk_div = div;
1199 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1200 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1203 if (mcbsp->active) {
1204 if (freq == mcbsp->in_freq)
1210 mcbsp->in_freq = freq;
1223 err = omap2_mcbsp_set_clks_src(mcbsp,
1231 err = omap2_mcbsp_set_clks_src(mcbsp,
1260 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1262 pm_runtime_enable(mcbsp->dev);
1265 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1266 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1273 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1275 pm_runtime_disable(mcbsp->dev);
1311 .name = "omap-mcbsp",
1342 .compatible = "ti,omap2420-mcbsp",
1346 .compatible = "ti,omap2430-mcbsp",
1350 .compatible = "ti,omap3-mcbsp",
1354 .compatible = "ti,omap4-mcbsp",
1366 struct omap_mcbsp *mcbsp;
1388 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1389 if (!mcbsp)
1392 mcbsp->id = pdev->id;
1393 mcbsp->pdata = pdata;
1394 mcbsp->dev = &pdev->dev;
1395 platform_set_drvdata(pdev, mcbsp);
1401 if (mcbsp->pdata->reg_size == 2) {
1417 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1419 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1420 mcbsp->pdata->ops->free(mcbsp->id);
1422 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1423 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1428 .name = "omap-mcbsp",
1441 MODULE_ALIAS("platform:omap-mcbsp");