Lines Matching refs:uc
240 static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
242 struct i2c_client *client = uc->client;
265 pm_runtime_get_sync(uc->dev);
273 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
274 pm_runtime_put_sync(uc->dev);
281 pm_runtime_put_sync(uc->dev);
285 static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
287 struct i2c_client *client = uc->client;
307 pm_runtime_get_sync(uc->dev);
310 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
311 pm_runtime_put_sync(uc->dev);
316 pm_runtime_put_sync(uc->dev);
321 static int ccg_op_region_update(struct ucsi_ccg *uc, u32 cci)
324 struct op_region *data = &uc->op_data;
332 int ret = ccg_read(uc, reg, (void *)buf, size);
340 spin_lock(&uc->op_lock);
344 spin_unlock(&uc->op_lock);
349 static int ucsi_ccg_init(struct ucsi_ccg *uc)
355 spin_lock_init(&uc->op_lock);
358 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
363 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
372 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
379 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
389 static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data)
394 new_cam = uc->orig[cam].linked_idx;
395 uc->updated[new_cam].active_idx = cam;
403 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
408 alt = uc->orig;
409 new_alt = uc->updated;
410 memset(uc->updated, 0, sizeof(uc->updated));
460 uc->has_multiple_dp = true;
475 static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc,
485 port = uc->orig;
487 new_port = &uc->updated[new_cam];
540 static void ucsi_ccg_nvidia_altmode(struct ucsi_ccg *uc,
543 switch (UCSI_ALTMODE_OFFSET(uc->last_cmd_sent)) {
562 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
569 spin_lock(&uc->op_lock);
570 memcpy(val, &(uc->op_data).cci, val_len);
571 spin_unlock(&uc->op_lock);
573 spin_lock(&uc->op_lock);
574 memcpy(val, &(uc->op_data).message_in, val_len);
575 spin_unlock(&uc->op_lock);
577 ret = ccg_read(uc, reg, val, val_len);
586 switch (UCSI_COMMAND(uc->last_cmd_sent)) {
588 if (uc->has_multiple_dp)
589 ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)val);
592 if (UCSI_ALTMODE_RECIPIENT(uc->last_cmd_sent) ==
596 ucsi_ccg_nvidia_altmode(uc, alt);
600 if (uc->fw_build == CCG_FW_BUILD_NVIDIA_TEGRA) {
608 uc->last_cmd_sent = 0;
616 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
623 spin_lock(&uc->op_lock);
624 uc->op_data.cci = 0;
625 spin_unlock(&uc->op_lock);
627 return ccg_write(uc, reg, val, val_len);
633 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
638 mutex_lock(&uc->lock);
639 pm_runtime_get_sync(uc->dev);
640 set_bit(DEV_CMD_PENDING, &uc->flags);
642 if (offset == UCSI_CONTROL && val_len == sizeof(uc->last_cmd_sent)) {
643 uc->last_cmd_sent = *(u64 *)val;
645 if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_SET_NEW_CAM &&
646 uc->has_multiple_dp) {
647 con_index = (uc->last_cmd_sent >> 16) &
649 con = &uc->ucsi->connector[con_index - 1];
650 ucsi_ccg_update_set_new_cam_cmd(uc, con, (u64 *)val);
658 if (!wait_for_completion_timeout(&uc->complete, msecs_to_jiffies(5000)))
662 clear_bit(DEV_CMD_PENDING, &uc->flags);
663 pm_runtime_put_sync(uc->dev);
664 mutex_unlock(&uc->lock);
679 struct ucsi_ccg *uc = data;
684 ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
693 ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
698 ucsi_connector_change(uc->ucsi, UCSI_CCI_CONNECTOR(cci));
704 ret = ccg_op_region_update(uc, cci);
709 ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
711 if (!ret && test_bit(DEV_CMD_PENDING, &uc->flags) &&
713 complete(&uc->complete);
718 static int ccg_request_irq(struct ucsi_ccg *uc)
722 if (!dev_fwnode(uc->dev))
725 return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc);
733 static int get_fw_info(struct ucsi_ccg *uc)
737 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
738 sizeof(uc->version));
742 uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
743 CCG_VERSION_PATCH(uc->version[FW2].app.patch);
745 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
746 sizeof(uc->info));
758 static void ccg_process_response(struct ucsi_ccg *uc)
760 struct device *dev = uc->dev;
762 if (uc->dev_resp.code & ASYNC_EVENT) {
763 if (uc->dev_resp.code == RESET_COMPLETE) {
764 if (test_bit(RESET_PENDING, &uc->flags))
765 uc->cmd_resp = uc->dev_resp.code;
766 get_fw_info(uc);
768 if (invalid_async_evt(uc->dev_resp.code))
770 uc->dev_resp.code);
772 if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
773 uc->cmd_resp = uc->dev_resp.code;
774 clear_bit(DEV_CMD_PENDING, &uc->flags);
777 uc->dev_resp.code);
782 static int ccg_read_response(struct ucsi_ccg *uc)
785 struct device *dev = uc->dev;
791 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
806 status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
807 sizeof(uc->dev_resp));
811 status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
818 /* Caller must hold uc->lock */
819 static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
821 struct device *dev = uc->dev;
826 set_bit(DEV_CMD_PENDING, &uc->flags);
833 ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
839 ret = ccg_read_response(uc);
844 clear_bit(DEV_CMD_PENDING, &uc->flags);
852 ccg_process_response(uc);
854 return uc->cmd_resp;
857 static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
867 mutex_lock(&uc->lock);
869 ret = ccg_send_command(uc, &cmd);
871 mutex_unlock(&uc->lock);
874 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
881 static int ccg_cmd_reset(struct ucsi_ccg *uc)
894 mutex_lock(&uc->lock);
896 set_bit(RESET_PENDING, &uc->flags);
898 ret = ccg_send_command(uc, &cmd);
905 clear_bit(RESET_PENDING, &uc->flags);
907 mutex_unlock(&uc->lock);
912 static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
919 cmd.data = (uc->port_num == 1) ?
926 mutex_lock(&uc->lock);
928 ret = ccg_send_command(uc, &cmd);
930 mutex_unlock(&uc->lock);
933 dev_err(uc->dev, "port control failed ret=%d\n", ret);
939 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
954 mutex_lock(&uc->lock);
956 set_bit(RESET_PENDING, &uc->flags);
958 ret = ccg_send_command(uc, &cmd);
965 clear_bit(RESET_PENDING, &uc->flags);
967 mutex_unlock(&uc->lock);
973 ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
976 struct i2c_client *client = uc->client;
987 mutex_lock(&uc->lock);
991 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
992 mutex_unlock(&uc->lock);
1009 ret = ccg_send_command(uc, &cmd);
1011 mutex_unlock(&uc->lock);
1014 dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
1021 static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
1031 mutex_lock(&uc->lock);
1033 ret = ccg_send_command(uc, &cmd);
1035 mutex_unlock(&uc->lock);
1043 static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
1047 struct device *dev = uc->dev;
1050 if (le16_to_cpu(app->build) != uc->fw_build) {
1056 if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
1063 static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
1067 struct device *dev = uc->dev;
1100 if (!ccg_check_vendor_version(uc, app, &fw_cfg))
1111 static int ccg_fw_update_needed(struct ucsi_ccg *uc,
1114 struct device *dev = uc->dev;
1118 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
1119 sizeof(uc->info));
1125 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
1145 } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
1156 static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
1158 struct device *dev = uc->dev;
1175 if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
1177 err = ccg_cmd_port_control(uc, false);
1180 err = ccg_cmd_jump_boot_mode(uc, 0);
1207 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
1212 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
1217 err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
1229 err = ccg_cmd_enter_flashing(uc);
1277 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
1289 err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1);
1297 err = ccg_cmd_port_control(uc, false);
1301 err = ccg_cmd_reset(uc);
1305 err = ccg_cmd_port_control(uc, true);
1323 static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
1328 err = do_flash(uc, flash_mode);
1331 err = ccg_fw_update_needed(uc, &flash_mode);
1335 dev_info(uc->dev, "CCG FW update successful\n");
1340 static int ccg_restart(struct ucsi_ccg *uc)
1342 struct device *dev = uc->dev;
1345 status = ucsi_ccg_init(uc);
1351 status = ccg_request_irq(uc);
1357 status = ucsi_register(uc->ucsi);
1359 dev_err(uc->dev, "failed to register the interface\n");
1363 pm_runtime_enable(uc->dev);
1369 struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
1373 status = ccg_fw_update_needed(uc, &flash_mode);
1378 ucsi_unregister(uc->ucsi);
1379 pm_runtime_disable(uc->dev);
1380 free_irq(uc->irq, uc);
1382 ccg_fw_update(uc, flash_mode);
1383 ccg_restart(uc);
1391 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1400 if (uc->fw_build == 0x0) {
1405 schedule_work(&uc->work);
1420 struct ucsi_ccg *uc;
1424 uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
1425 if (!uc)
1428 uc->dev = dev;
1429 uc->client = client;
1430 uc->irq = client->irq;
1431 mutex_init(&uc->lock);
1432 init_completion(&uc->complete);
1433 INIT_WORK(&uc->work, ccg_update_firmware);
1434 INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
1440 uc->fw_build = CCG_FW_BUILD_NVIDIA_TEGRA;
1442 uc->fw_build = CCG_FW_BUILD_NVIDIA;
1445 if (!uc->fw_build)
1446 dev_err(uc->dev, "failed to get FW build information\n");
1449 status = ucsi_ccg_init(uc);
1451 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
1455 status = get_fw_info(uc);
1457 dev_err(uc->dev, "get_fw_info failed - %d\n", status);
1461 uc->port_num = 1;
1463 if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
1464 uc->port_num++;
1466 uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
1467 if (IS_ERR(uc->ucsi))
1468 return PTR_ERR(uc->ucsi);
1470 ucsi_set_drvdata(uc->ucsi, uc);
1472 status = ccg_request_irq(uc);
1474 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
1478 status = ucsi_register(uc->ucsi);
1482 i2c_set_clientdata(client, uc);
1484 pm_runtime_set_active(uc->dev);
1485 pm_runtime_enable(uc->dev);
1486 pm_runtime_use_autosuspend(uc->dev);
1487 pm_runtime_set_autosuspend_delay(uc->dev, 5000);
1488 pm_runtime_idle(uc->dev);
1493 free_irq(uc->irq, uc);
1495 ucsi_destroy(uc->ucsi);
1502 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1504 cancel_work_sync(&uc->pm_work);
1505 cancel_work_sync(&uc->work);
1506 pm_runtime_disable(uc->dev);
1507 ucsi_unregister(uc->ucsi);
1508 ucsi_destroy(uc->ucsi);
1509 free_irq(uc->irq, uc);
1533 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1535 return ucsi_resume(uc->ucsi);
1546 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1553 if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
1554 uc->fw_version <= CCG_OLD_FW_VERSION)
1555 schedule_work(&uc->pm_work);