Lines Matching refs:ep
174 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
181 #define UDC_EPIN_IDX(ep) (ep * 2)
182 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
270 * @ep: embedded ep request
276 * @offset_addr: offset address of ep register
284 struct usb_ep ep;
319 * @ep: array of endpoints
342 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
380 * @req: embedded ep request
425 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
427 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
430 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
433 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
436 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
440 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
443 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
447 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
470 * @ep: end-point number
473 unsigned int ep)
475 unsigned long reg = PCH_UDC_CSR(ep);
485 * @ep: end-point number
489 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
491 unsigned long reg = PCH_UDC_CSR(ep);
616 * @ep: Reference to structure of type pch_udc_ep_regs
618 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
620 if (ep->in) {
621 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
622 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
624 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
630 * @ep: Reference to structure of type pch_udc_ep_regs
632 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
635 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
637 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
642 * @ep: Reference to structure of type pch_udc_ep_regs
645 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
648 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
654 * @ep: Reference to structure of type pch_udc_ep_regs
658 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
663 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
665 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
667 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
669 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
675 * @ep: Reference to structure of type pch_udc_ep_regs
678 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
680 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
682 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
687 * @ep: Reference to structure of type pch_udc_ep_regs
690 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
692 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
697 * @ep: Reference to structure of type pch_udc_ep_regs
700 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
702 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
707 * @ep: Reference to structure of type pch_udc_ep_regs
709 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
711 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
716 * @ep: Reference to structure of type pch_udc_ep_regs
718 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
720 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
725 * @ep: Reference to structure of type pch_udc_ep_regs
727 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
729 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
872 * @ep: Reference to structure of type pch_udc_ep_regs
875 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
877 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
882 * @ep: Reference to structure of type pch_udc_ep_regs
885 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
887 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
892 * @ep: Reference to structure of type pch_udc_ep_regs
895 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
897 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
902 * @ep: Reference to structure of type pch_udc_ep_regs
905 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
908 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
914 * @ep: Reference to structure of type pch_udc_ep_regs
916 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
918 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
924 * @ep: reference to structure of type pch_udc_ep_regs
926 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
929 struct pch_udc_dev *dev = ep->dev;
931 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
933 if (!ep->in) {
935 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
943 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
944 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
948 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
949 __func__, ep->num, (ep->in ? "in" : "out"));
954 * @ep: reference to structure of type pch_udc_ep_regs
959 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
961 if (dir) { /* IN ep */
962 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
969 * @ep: reference to structure of type pch_udc_ep_regs
973 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
980 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
981 if (ep->in)
985 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
986 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
987 pch_udc_ep_set_nak(ep);
988 pch_udc_ep_fifo_flush(ep, ep->in);
990 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
998 if (ep->in)
999 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1001 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1006 * @ep: reference to structure of type pch_udc_ep_regs
1008 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1010 if (ep->in) {
1012 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1014 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1015 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1018 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1021 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1026 * @ep: reference to structure of type pch_udc_ep_regs
1028 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1033 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1036 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1060 /* mask and clear all ep interrupts */
1086 /* mask all ep interrupts */
1417 * @ep: Reference to the endpoint structure
1421 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1427 unsigned halted = ep->halted;
1437 dev = ep->dev;
1438 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
1439 ep->halted = 1;
1441 if (!ep->in)
1442 pch_udc_ep_clear_rrdy(ep);
1443 usb_gadget_giveback_request(&ep->ep, &req->req);
1445 ep->halted = halted;
1450 * @ep: Reference to the endpoint structure
1452 static void empty_req_queue(struct pch_udc_ep *ep)
1456 ep->halted = 1;
1457 while (!list_empty(&ep->queue)) {
1458 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1459 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1494 * @ep: Reference to the endpoint structure
1503 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1514 pch_udc_free_dma_chain(ep->dev, req);
1524 td = dma_pool_alloc(ep->dev->data_requests, gfp_flags,
1542 pch_udc_free_dma_chain(ep->dev, req);
1551 * @ep: Reference to the endpoint structure
1559 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1565 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1570 if (ep->in)
1579 * @ep: Reference to the endpoint structure
1582 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1584 struct pch_udc_dev *dev = ep->dev;
1587 complete_req(ep, req, 0);
1598 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1605 * @ep: Reference to the endpoint structure
1608 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1613 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1624 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1626 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1627 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1628 pch_udc_ep_clear_nak(ep);
1629 pch_udc_ep_set_rrdy(ep);
1646 struct pch_udc_ep *ep;
1654 ep = container_of(usbep, struct pch_udc_ep, ep);
1655 dev = ep->dev;
1659 ep->ep.desc = desc;
1660 ep->halted = 0;
1661 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1662 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1663 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1679 struct pch_udc_ep *ep;
1685 ep = container_of(usbep, struct pch_udc_ep, ep);
1686 if ((usbep->name == ep0_string) || !ep->ep.desc)
1689 spin_lock_irqsave(&ep->dev->lock, iflags);
1690 empty_req_queue(ep);
1691 ep->halted = 1;
1692 pch_udc_ep_disable(ep);
1693 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1694 ep->ep.desc = NULL;
1695 INIT_LIST_HEAD(&ep->queue);
1696 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1714 struct pch_udc_ep *ep;
1719 ep = container_of(usbep, struct pch_udc_ep, ep);
1725 if (!ep->dev->dma_addr)
1728 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
1752 struct pch_udc_ep *ep;
1758 ep = container_of(usbep, struct pch_udc_ep, ep);
1760 dev = ep->dev;
1766 pch_udc_free_dma_chain(ep->dev, req);
1767 dma_pool_free(ep->dev->data_requests, req->td_data,
1788 struct pch_udc_ep *ep;
1795 ep = container_of(usbep, struct pch_udc_ep, ep);
1796 dev = ep->dev;
1797 if (!ep->ep.desc && ep->num)
1806 retval = usb_gadget_map_request(&dev->gadget, usbreq, ep->in);
1810 retval = prepare_dma(ep, req, GFP_ATOMIC);
1817 if (list_empty(&ep->queue) && !ep->halted) {
1820 process_zlp(ep, req);
1824 if (!ep->in) {
1825 pch_udc_start_rxrequest(ep, req);
1832 pch_udc_wait_ep_stall(ep);
1833 pch_udc_ep_clear_nak(ep);
1834 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1837 /* Now add this request to the ep's pending requests */
1839 list_add_tail(&req->queue, &ep->queue);
1859 struct pch_udc_ep *ep;
1864 ep = container_of(usbep, struct pch_udc_ep, ep);
1865 if (!usbep || !usbreq || (!ep->ep.desc && ep->num))
1868 spin_lock_irqsave(&ep->dev->lock, flags);
1870 list_for_each_entry(req, &ep->queue, queue) {
1872 pch_udc_ep_set_nak(ep);
1874 complete_req(ep, req, -ECONNRESET);
1879 spin_unlock_irqrestore(&ep->dev->lock, flags);
1895 struct pch_udc_ep *ep;
1901 ep = container_of(usbep, struct pch_udc_ep, ep);
1902 if (!ep->ep.desc && !ep->num)
1904 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1907 if (list_empty(&ep->queue)) {
1909 if (ep->num == PCH_UDC_EP0)
1910 ep->dev->stall = 1;
1911 pch_udc_ep_set_stall(ep);
1913 ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1915 pch_udc_ep_clear_stall(ep);
1936 struct pch_udc_ep *ep;
1942 ep = container_of(usbep, struct pch_udc_ep, ep);
1943 if (!ep->ep.desc && !ep->num)
1945 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1948 if (!list_empty(&ep->queue)) {
1951 if (ep->num == PCH_UDC_EP0)
1952 ep->dev->stall = 1;
1953 pch_udc_ep_set_stall(ep);
1954 pch_udc_enable_ep_interrupts(ep->dev,
1955 PCH_UDC_EPINT(ep->in, ep->num));
1956 ep->dev->prot_stall = 1;
1969 struct pch_udc_ep *ep;
1974 ep = container_of(usbep, struct pch_udc_ep, ep);
1975 if (ep->ep.desc || !ep->num)
1976 pch_udc_ep_fifo_flush(ep, ep->in);
2010 * @ep: Reference to the endpoint structure
2012 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2017 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2020 if (list_empty(&ep->queue))
2024 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2029 pch_udc_wait_ep_stall(ep);
2031 pch_udc_ep_set_ddptr(ep, 0);
2040 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2041 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2042 pch_udc_ep_set_pd(ep);
2043 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2044 pch_udc_ep_clear_nak(ep);
2049 * @ep: Reference to the endpoint structure
2051 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2054 struct pch_udc_dev *dev = ep->dev;
2056 if (list_empty(&ep->queue))
2058 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2067 (int)(ep->epsts));
2074 complete_req(ep, req, 0);
2076 if (!list_empty(&ep->queue)) {
2077 pch_udc_wait_ep_stall(ep);
2078 pch_udc_ep_clear_nak(ep);
2079 pch_udc_enable_ep_interrupts(ep->dev,
2080 PCH_UDC_EPINT(ep->in, ep->num));
2082 pch_udc_disable_ep_interrupts(ep->dev,
2083 PCH_UDC_EPINT(ep->in, ep->num));
2089 * @ep: Reference to the endpoint structure
2091 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2094 struct pch_udc_dev *dev = ep->dev;
2099 if (list_empty(&ep->queue))
2102 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2103 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2104 pch_udc_ep_set_ddptr(ep, 0);
2116 (int)(ep->epsts));
2139 complete_req(ep, req, 0);
2141 if (!list_empty(&ep->queue)) {
2142 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2143 pch_udc_start_rxrequest(ep, req);
2156 struct pch_udc_ep *ep;
2158 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2159 epsts = ep->epsts;
2160 ep->epsts = 0;
2171 pch_udc_ep_set_stall(ep);
2172 pch_udc_enable_ep_interrupts(ep->dev,
2173 PCH_UDC_EPINT(ep->in, ep->num));
2177 pch_udc_ep_clear_stall(ep);
2179 pch_udc_ep_set_stall(ep);
2180 pch_udc_enable_ep_interrupts(ep->dev,
2181 PCH_UDC_EPINT(ep->in, ep->num));
2185 pch_udc_complete_transfer(ep);
2189 pch_udc_start_next_txrequest(ep);
2200 struct pch_udc_ep *ep;
2203 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2204 epsts = ep->epsts;
2205 ep->epsts = 0;
2207 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2209 req = list_entry(ep->queue.next, struct pch_udc_request,
2214 pch_udc_start_rxrequest(ep, req);
2221 pch_udc_ep_set_stall(ep);
2222 pch_udc_enable_ep_interrupts(ep->dev,
2223 PCH_UDC_EPINT(ep->in, ep->num));
2227 pch_udc_ep_clear_stall(ep);
2229 pch_udc_ep_set_stall(ep);
2230 pch_udc_enable_ep_interrupts(ep->dev,
2231 PCH_UDC_EPINT(ep->in, ep->num));
2236 if (ep->dev->prot_stall == 1) {
2237 pch_udc_ep_set_stall(ep);
2238 pch_udc_enable_ep_interrupts(ep->dev,
2239 PCH_UDC_EPINT(ep->in, ep->num));
2241 pch_udc_complete_receiver(ep);
2244 if (list_empty(&ep->queue))
2270 struct pch_udc_ep *ep;
2273 ep = &dev->ep[UDC_EP0IN_IDX];
2274 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2275 epsts = ep->epsts;
2276 ep->epsts = 0;
2287 pch_udc_complete_transfer(ep);
2299 pch_udc_start_next_txrequest(ep);
2313 struct pch_udc_ep *ep;
2315 ep = &dev->ep[UDC_EP0OUT_IDX];
2316 stat = ep->epsts;
2317 ep->epsts = 0;
2323 dev->ep[UDC_EP0IN_IDX].halted = 0;
2324 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2325 dev->setup_data = ep->td_stp->request;
2326 pch_udc_init_setup_buff(ep->td_stp);
2328 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2329 dev->ep[UDC_EP0IN_IDX].in);
2331 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2333 dev->gadget.ep0 = &ep->ep;
2342 ep->td_data->status = (ep->td_data->status &
2345 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2350 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2355 pch_udc_ep_clear_nak(ep);
2359 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2360 pch_udc_enable_ep_interrupts(ep->dev,
2361 PCH_UDC_EPINT(ep->in, ep->num));
2370 pch_udc_ep_set_ddptr(ep, 0);
2371 if (!list_empty(&ep->queue)) {
2372 ep->epsts = stat;
2377 pch_udc_ep_set_rrdy(ep);
2389 struct pch_udc_ep *ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2390 if (list_empty(&ep->queue))
2392 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2393 pch_udc_ep_clear_nak(ep);
2404 struct pch_udc_ep *ep;
2409 ep = &dev->ep[UDC_EPIN_IDX(i)];
2410 ep->epsts = pch_udc_read_ep_status(ep);
2411 pch_udc_clear_ep_status(ep, ep->epsts);
2415 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2416 ep->epsts = pch_udc_read_ep_status(ep);
2417 pch_udc_clear_ep_status(ep, ep->epsts);
2429 struct pch_udc_ep *ep;
2433 ep = &dev->ep[UDC_EP0IN_IDX];
2434 pch_udc_clear_ep_control(ep);
2435 pch_udc_ep_fifo_flush(ep, ep->in);
2436 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2437 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2439 ep->td_data = NULL;
2440 ep->td_stp = NULL;
2441 ep->td_data_phys = 0;
2442 ep->td_stp_phys = 0;
2445 ep = &dev->ep[UDC_EP0OUT_IDX];
2446 pch_udc_clear_ep_control(ep);
2447 pch_udc_ep_fifo_flush(ep, ep->in);
2448 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2449 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2451 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2454 pch_udc_init_setup_buff(ep->td_stp);
2456 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2458 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2461 ep->td_data->status = PCH_UDC_DMA_LAST;
2462 ep->td_data->dataptr = dev->dma_addr;
2463 ep->td_data->next = ep->td_data_phys;
2465 pch_udc_ep_clear_nak(ep);
2475 struct pch_udc_ep *ep;
2486 ep = &dev->ep[i];
2487 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2488 pch_udc_clear_ep_control(ep);
2489 pch_udc_ep_set_ddptr(ep, 0);
2490 pch_udc_write_csr(ep->dev, 0x00, i);
2497 /* disable ep to empty req queue. Skip the control EP's */
2499 ep = &dev->ep[i];
2500 pch_udc_ep_set_nak(ep);
2501 pch_udc_ep_fifo_flush(ep, ep->in);
2503 empty_req_queue(ep);
2543 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2583 pch_udc_ep_clear_stall(&(dev->ep[i]));
2584 dev->ep[i].halted = 0;
2616 pch_udc_ep_clear_stall(&(dev->ep[i]));
2617 dev->ep[i].halted = 0;
2713 /* Clear ep interrupts */
2783 memset(dev->ep, 0, sizeof dev->ep);
2785 struct pch_udc_ep *ep = &dev->ep[i];
2786 ep->dev = dev;
2787 ep->halted = 1;
2788 ep->num = i / 2;
2789 ep->in = ~i & 1;
2790 ep->ep.name = ep_string[i];
2791 ep->ep.ops = &pch_udc_ep_ops;
2792 if (ep->in) {
2793 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2794 ep->ep.caps.dir_in = true;
2796 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2798 ep->ep.caps.dir_out = true;
2801 ep->ep.caps.type_control = true;
2803 ep->ep.caps.type_iso = true;
2804 ep->ep.caps.type_bulk = true;
2805 ep->ep.caps.type_int = true;
2807 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2808 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE);
2809 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2810 INIT_LIST_HEAD(&ep->queue);
2812 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE);
2813 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE);
2816 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2817 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2819 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2873 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2879 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2883 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2889 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2890 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2891 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2892 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2893 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2997 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2999 dev->ep[UDC_EP0OUT_IDX].td_stp,
3000 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3002 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3004 dev->ep[UDC_EP0OUT_IDX].td_data,
3005 dev->ep[UDC_EP0OUT_IDX].td_data_phys);