drivers/spi/spi-topcliff-pch.c

127  * @host:			Pointer to the SPI controller structure
164 	struct spi_controller *host;
219  * @host:	Pointer to struct spi_controller.
223 static inline void pch_spi_writereg(struct spi_controller *host, int idx, u32 val)
225 	struct pch_spi_data *data = spi_controller_get_devdata(host);
231  * @host:	Pointer to struct spi_controller.
234 static inline u32 pch_spi_readreg(struct spi_controller *host, int idx)
236 	struct pch_spi_data *data = spi_controller_get_devdata(host);
240 static inline void pch_spi_setclr_reg(struct spi_controller *host, int idx,
243 	u32 tmp = pch_spi_readreg(host, idx);
245 	pch_spi_writereg(host, idx, tmp);
248 static void pch_spi_set_host_mode(struct spi_controller *host)
250 	pch_spi_setclr_reg(host, PCH_SPCR, SPCR_MSTR_BIT, 0);
255  * @host:	Pointer to struct spi_controller.
257 static void pch_spi_clear_fifo(struct spi_controller *host)
259 	pch_spi_setclr_reg(host, PCH_SPCR, SPCR_FICLR_BIT, 0);
260 	pch_spi_setclr_reg(host, PCH_SPCR, 0, SPCR_FICLR_BIT);
315 				pch_spi_setclr_reg(data->host, PCH_SPCR, 0,
324 				dev_vdbg(&data->host->dev,
386  * @host:	Pointer to struct spi_controller.
389 static void pch_spi_set_baud_rate(struct spi_controller *host, u32 speed_hz)
397 	pch_spi_setclr_reg(host, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
402  * @host:		Pointer to struct spi_controller.
405 static void pch_spi_set_bits_per_word(struct spi_controller *host,
409 		pch_spi_setclr_reg(host, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
411 		pch_spi_setclr_reg(host, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
445  * @host:	Pointer to struct spi_controller.
447 static void pch_spi_reset(struct spi_controller *host)
450 	pch_spi_writereg(host, PCH_SRST, 0x1);
453 	pch_spi_writereg(host, PCH_SRST, 0x0);
527 		dev_dbg(&data->host->dev, "%s:setting baud rate\n", __func__);
528 		pch_spi_set_baud_rate(data->host, data->cur_trans->speed_hz);
534 		dev_dbg(&data->host->dev, "%s:set bits per word\n", __func__);
535 		pch_spi_set_bits_per_word(data->host,
593 	dev_dbg(&data->host->dev,
596 	pch_spi_writereg(data->host, PCH_SSNXCR, SSN_LOW);
599 		pch_spi_writereg(data->host, PCH_SPDWR, data->pkt_tx_buff[j]);
612 	dev_dbg(&data->host->dev, "%s called\n", __func__);
618 		dev_dbg(&data->host->dev,
626 	dev_dbg(&data->host->dev,
641 		dev_dbg(&data->host->dev, "%s:Invoke queue_work\n", __func__);
645 		dev_dbg(&data->host->dev,
665 		pch_spi_setclr_reg(data->host, PCH_SPCR,
672 		pch_spi_setclr_reg(data->host, PCH_SPCR,
680 	dev_dbg(&data->host->dev,
686 	pch_spi_writereg(data->host, PCH_SPSR,
687 			 pch_spi_readreg(data->host, PCH_SPSR));
689 	pch_spi_setclr_reg(data->host, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
691 	pch_spi_clear_fifo(data->host);
753 	pch_spi_setclr_reg(data->host, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
759 	dev_dbg(&data->host->dev,
765 		dev_err(&data->host->dev,
768 	dma_sync_sg_for_cpu(&data->host->dev, dma->sg_rx_p, dma->nent,
771 	dma_sync_sg_for_cpu(&data->host->dev, dma->sg_tx_p, dma->nent,
783 	pch_spi_setclr_reg(data->host, PCH_SPCR, 0,
787 	pch_spi_writereg(data->host, PCH_SPSR,
788 			 pch_spi_readreg(data->host, PCH_SPSR));
790 	pch_spi_clear_fifo(data->host);
849 		dev_err(&data->host->dev,
863 		dev_err(&data->host->dev,
916 		dev_dbg(&data->host->dev, "%s:setting baud rate\n", __func__);
918 		pch_spi_set_baud_rate(data->host, data->cur_trans->speed_hz);
926 		dev_dbg(&data->host->dev, "%s:set bits per word\n", __func__);
928 		pch_spi_set_bits_per_word(data->host,
972 	dev_dbg(&data->host->dev, "%s num=%d size=%d rem=%d\n",
977 	pch_spi_setclr_reg(data->host, PCH_SPCR,
1019 		dev_err(&data->host->dev,
1023 	dma_sync_sg_for_device(&data->host->dev, sg, num, DMA_FROM_DEVICE);
1081 		dev_err(&data->host->dev,
1085 	dma_sync_sg_for_device(&data->host->dev, sg, num, DMA_TO_DEVICE);
1091 	dev_dbg(&data->host->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1094 	pch_spi_writereg(data->host, PCH_SSNXCR, SSN_LOW);
1110 	dev_dbg(&data->host->dev, "%s data initialized\n", __func__);
1115 		dev_dbg(&data->host->dev,
1135 	dev_dbg(&data->host->dev,
1153 	pch_spi_writereg(data->host, PCH_SSNXCR, SSN_NO_CONTROL);
1164 			dev_dbg(&data->host->dev,
1171 			dev_dbg(&data->host->dev,
1213 		dev_dbg(&data->host->dev,
1232 	pch_spi_writereg(data->host, PCH_SSNXCR, SSN_HIGH);
1251 	pch_spi_reset(data->host);
1300 	struct spi_controller *host;
1306 	host = spi_alloc_host(&board_dat->pdev->dev,
1308 	if (!host) {
1314 	data = spi_controller_get_devdata(host);
1315 	data->host = host;
1333 	/* initialize members of SPI host */
1334 	host->num_chipselect = PCH_MAX_CS;
1335 	host->transfer = pch_spi_transfer;
1336 	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1337 	host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1338 	host->max_speed_hz = PCH_MAX_BAUDRATE;
1339 	host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1368 	pch_spi_set_host_mode(host);
1377 	ret = spi_register_controller(host);
1394 	spi_controller_put(host);
1430 		pch_spi_setclr_reg(data->host, PCH_SPCR, 0, PCH_ALL);
1436 	spi_unregister_controller(data->host);
1466 		pch_spi_setclr_reg(data->host, PCH_SPCR, 0, PCH_ALL);
1467 		pch_spi_reset(data->host);
1501 		pch_spi_reset(data->host);
1502 		pch_spi_set_host_mode(data->host);