drivers/spi/spi-sprd.c

168 	int (*read_bufs)(struct sprd_spi *ss, u32 len);
169 	int (*write_bufs)(struct sprd_spi *ss, u32 len);
172 static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
180 	u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz);
186 	u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay;
188 					    ss->src_clk);
193 static int sprd_spi_wait_for_tx_end(struct sprd_spi *ss, struct spi_transfer *t)
198 	us = sprd_spi_transfer_max_timeout(ss, t);
199 	ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
202 		dev_err(ss->dev, "SPI error, spi send timeout!\n");
206 	ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
209 		dev_err(ss->dev, "SPI error, spi busy timeout!\n");
213 	writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
218 static int sprd_spi_wait_for_rx_end(struct sprd_spi *ss, struct spi_transfer *t)
223 	us = sprd_spi_transfer_max_timeout(ss, t);
224 	ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
227 		dev_err(ss->dev, "SPI error, spi rx timeout!\n");
231 	writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
236 static void sprd_spi_tx_req(struct sprd_spi *ss)
238 	writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12);
241 static void sprd_spi_rx_req(struct sprd_spi *ss)
243 	writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12);
246 static void sprd_spi_enter_idle(struct sprd_spi *ss)
248 	u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
251 	writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
254 static void sprd_spi_set_transfer_bits(struct sprd_spi *ss, u32 bits)
256 	u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
261 	writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
264 static void sprd_spi_set_tx_length(struct sprd_spi *ss, u32 length)
266 	u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
271 	writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
274 	writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
277 static void sprd_spi_set_rx_length(struct sprd_spi *ss, u32 length)
279 	u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
284 	writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
287 	writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
293 	struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
296 	val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
300 		writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
303 		writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
307 static int sprd_spi_write_only_receive(struct sprd_spi *ss, u32 len)
312 	val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
314 	writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
317 	val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
319 	writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
322 	val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
324 	writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
329 static int sprd_spi_write_bufs_u8(struct sprd_spi *ss, u32 len)
331 	u8 *tx_p = (u8 *)ss->tx_buf;
335 		writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
337 	ss->tx_buf += i;
341 static int sprd_spi_write_bufs_u16(struct sprd_spi *ss, u32 len)
343 	u16 *tx_p = (u16 *)ss->tx_buf;
347 		writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
349 	ss->tx_buf += i << 1;
353 static int sprd_spi_write_bufs_u32(struct sprd_spi *ss, u32 len)
355 	u32 *tx_p = (u32 *)ss->tx_buf;
359 		writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
361 	ss->tx_buf += i << 2;
365 static int sprd_spi_read_bufs_u8(struct sprd_spi *ss, u32 len)
367 	u8 *rx_p = (u8 *)ss->rx_buf;
371 		rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD);
373 	ss->rx_buf += i;
377 static int sprd_spi_read_bufs_u16(struct sprd_spi *ss, u32 len)
379 	u16 *rx_p = (u16 *)ss->rx_buf;
383 		rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD);
385 	ss->rx_buf += i << 1;
389 static int sprd_spi_read_bufs_u32(struct sprd_spi *ss, u32 len)
391 	u32 *rx_p = (u32 *)ss->rx_buf;
395 		rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD);
397 	ss->rx_buf += i << 2;
403 	struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
404 	u32 trans_len = ss->trans_len, len;
410 		if (ss->trans_mode & SPRD_SPI_TX_MODE) {
411 			sprd_spi_set_tx_length(ss, len);
412 			write_size += ss->write_bufs(ss, len);
418 			if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
419 				sprd_spi_tx_req(ss);
421 			ret = sprd_spi_wait_for_tx_end(ss, t);
423 			sprd_spi_set_rx_length(ss, len);
429 			if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
430 				sprd_spi_rx_req(ss);
432 				write_size += ss->write_bufs(ss, len);
434 			ret = sprd_spi_wait_for_rx_end(ss, t);
440 		if (ss->trans_mode & SPRD_SPI_RX_MODE)
441 			read_size += ss->read_bufs(ss, len);
446 	if (ss->trans_mode & SPRD_SPI_TX_MODE)
451 	sprd_spi_enter_idle(ss);
456 static void sprd_spi_irq_enable(struct sprd_spi *ss)
462 		ss->base + SPRD_SPI_INT_CLR);
464 	val = readl_relaxed(ss->base + SPRD_SPI_INT_EN);
467 		       ss->base + SPRD_SPI_INT_EN);
470 static void sprd_spi_irq_disable(struct sprd_spi *ss)
472 	writel_relaxed(0, ss->base + SPRD_SPI_INT_EN);
475 static void sprd_spi_dma_enable(struct sprd_spi *ss, bool enable)
477 	u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2);
484 	writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
516 static int sprd_spi_dma_rx_config(struct sprd_spi *ss, struct spi_transfer *t)
518 	struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_RX];
520 		.src_addr = ss->phy_base,
521 		.src_addr_width = ss->dma.width,
522 		.dst_addr_width = ss->dma.width,
523 		.dst_maxburst = ss->dma.fragmens_len,
531 	return ss->dma.rx_len;
534 static int sprd_spi_dma_tx_config(struct sprd_spi *ss, struct spi_transfer *t)
536 	struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_TX];
538 		.dst_addr = ss->phy_base,
539 		.src_addr_width = ss->dma.width,
540 		.dst_addr_width = ss->dma.width,
541 		.src_maxburst = ss->dma.fragmens_len,
552 static int sprd_spi_dma_request(struct sprd_spi *ss)
554 	ss->dma.dma_chan[SPRD_SPI_RX] = dma_request_chan(ss->dev, "rx_chn");
555 	if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_RX]))
556 		return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]),
559 	ss->dma.dma_chan[SPRD_SPI_TX]  = dma_request_chan(ss->dev, "tx_chn");
560 	if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_TX])) {
561 		dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
562 		return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]),
569 static void sprd_spi_dma_release(struct sprd_spi *ss)
571 	if (ss->dma.dma_chan[SPRD_SPI_RX])
572 		dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
574 	if (ss->dma.dma_chan[SPRD_SPI_TX])
575 		dma_release_channel(ss->dma.dma_chan[SPRD_SPI_TX]);
581 	struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
582 	u32 trans_len = ss->trans_len;
585 	reinit_completion(&ss->xfer_completion);
586 	sprd_spi_irq_enable(ss);
587 	if (ss->trans_mode & SPRD_SPI_TX_MODE) {
588 		write_size = sprd_spi_dma_tx_config(ss, t);
589 		sprd_spi_set_tx_length(ss, trans_len);
595 		if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
596 			sprd_spi_tx_req(ss);
598 		sprd_spi_set_rx_length(ss, trans_len);
604 		if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
605 			sprd_spi_rx_req(ss);
607 			write_size = ss->write_bufs(ss, trans_len);
612 		dev_err(ss->dev, "failed to write, ret = %d\n", ret);
616 	if (ss->trans_mode & SPRD_SPI_RX_MODE) {
624 		ss->dma.rx_len = t->len > ss->dma.fragmens_len ?
625 			(t->len - t->len % ss->dma.fragmens_len) :
627 		ret = sprd_spi_dma_rx_config(ss, t);
635 	sprd_spi_dma_enable(ss, true);
636 	wait_for_completion(&(ss->xfer_completion));
638 	if (ss->trans_mode & SPRD_SPI_TX_MODE)
641 		ret = ss->dma.rx_len;
644 	sprd_spi_dma_enable(ss, false);
645 	sprd_spi_enter_idle(ss);
646 	sprd_spi_irq_disable(ss);
651 static void sprd_spi_set_speed(struct sprd_spi *ss, u32 speed_hz)
657 	u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1;
660 	ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1);
661 	writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD);
664 static int sprd_spi_init_hw(struct sprd_spi *ss, struct spi_transfer *t)
673 	val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
676 	val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
677 	val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
678 	writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
688 	ss->word_delay = interval * 4 + 10;
689 	writel_relaxed(interval, ss->base + SPRD_SPI_CTL5);
692 	writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST);
693 	writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST);
696 	val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
699 	if (ss->hw_mode & SPI_3WIRE)
704 	if (ss->hw_mode & SPI_TX_DUAL)
709 	writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
717 	struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
722 	ss->len = t->len;
723 	ss->tx_buf = t->tx_buf;
724 	ss->rx_buf = t->rx_buf;
726 	ss->hw_mode = sdev->mode;
727 	ret = sprd_spi_init_hw(ss, t);
732 	sprd_spi_set_speed(ss, t->speed_hz);
733 	sprd_spi_set_transfer_bits(ss, bits_per_word);
742 		ss->trans_len = t->len;
743 		ss->read_bufs = sprd_spi_read_bufs_u8;
744 		ss->write_bufs = sprd_spi_write_bufs_u8;
745 		ss->dma.width = DMA_SLAVE_BUSWIDTH_1_BYTE;
746 		ss->dma.fragmens_len = SPRD_SPI_DMA_STEP;
749 		ss->trans_len = t->len >> 1;
750 		ss->read_bufs = sprd_spi_read_bufs_u16;
751 		ss->write_bufs = sprd_spi_write_bufs_u16;
752 		ss->dma.width = DMA_SLAVE_BUSWIDTH_2_BYTES;
753 		ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 1;
756 		ss->trans_len = t->len >> 2;
757 		ss->read_bufs = sprd_spi_read_bufs_u32;
758 		ss->write_bufs = sprd_spi_write_bufs_u32;
759 		ss->dma.width = DMA_SLAVE_BUSWIDTH_4_BYTES;
760 		ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 2;
767 	val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
774 	writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
776 	ss->trans_mode = mode;
782 	if (ss->trans_mode == SPRD_SPI_RX_MODE)
783 		ss->write_bufs = sprd_spi_write_only_receive;
816 	struct sprd_spi *ss = (struct sprd_spi *)data;
817 	u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS);
820 		writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
821 		if (!(ss->trans_mode & SPRD_SPI_RX_MODE))
822 			complete(&ss->xfer_completion);
828 		writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
829 		if (ss->dma.rx_len < ss->len) {
830 			ss->rx_buf += ss->dma.rx_len;
831 			ss->dma.rx_len +=
832 				ss->read_bufs(ss, ss->len - ss->dma.rx_len);
834 		complete(&ss->xfer_completion);
842 static int sprd_spi_irq_init(struct platform_device *pdev, struct sprd_spi *ss)
846 	ss->irq = platform_get_irq(pdev, 0);
847 	if (ss->irq < 0)
848 		return ss->irq;
850 	ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq,
851 				0, pdev->name, ss);
854 			ss->irq, ret);
859 static int sprd_spi_clk_init(struct platform_device *pdev, struct sprd_spi *ss)
875 	ss->clk = devm_clk_get(&pdev->dev, "enable");
876 	if (IS_ERR(ss->clk)) {
878 		return PTR_ERR(ss->clk);
882 		ss->src_clk = clk_get_rate(clk_spi);
884 		ss->src_clk = SPRD_SPI_DEFAULT_SOURCE;
892 	struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
894 	return ss->dma.enable && (t->len > SPRD_SPI_FIFO_SIZE);
897 static int sprd_spi_dma_init(struct platform_device *pdev, struct sprd_spi *ss)
901 	ret = sprd_spi_dma_request(ss);
913 	ss->dma.enable = true;
922 	struct sprd_spi *ss;
926 	sctlr = spi_alloc_host(&pdev->dev, sizeof(*ss));
930 	ss = spi_controller_get_devdata(sctlr);
931 	ss->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
932 	if (IS_ERR(ss->base)) {
933 		ret = PTR_ERR(ss->base);
937 	ss->phy_base = res->start;
938 	ss->dev = &pdev->dev;
946 	sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1,
949 	init_completion(&ss->xfer_completion);
951 	ret = sprd_spi_clk_init(pdev, ss);
955 	ret = sprd_spi_irq_init(pdev, ss);
959 	ret = sprd_spi_dma_init(pdev, ss);
963 	ret = clk_prepare_enable(ss->clk);
994 	clk_disable_unprepare(ss->clk);
996 	sprd_spi_dma_release(ss);
1006 	struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1009 	ret = pm_runtime_get_sync(ss->dev);
1011 		dev_err(ss->dev, "failed to resume SPI controller\n");
1016 		if (ss->dma.enable)
1017 			sprd_spi_dma_release(ss);
1018 		clk_disable_unprepare(ss->clk);
1027 	struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1029 	if (ss->dma.enable)
1030 		sprd_spi_dma_release(ss);
1032 	clk_disable_unprepare(ss->clk);
1040 	struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1043 	ret = clk_prepare_enable(ss->clk);
1047 	if (!ss->dma.enable)
1050 	ret = sprd_spi_dma_request(ss);
1052 		clk_disable_unprepare(ss->clk);