Lines Matching defs:drv_data
88 /* LPSS offset from drv_data->ioaddr */
90 /* Register offsets from drv_data->lpss_base or -1 */
181 *lpss_get_config(const struct driver_data *drv_data)
183 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
186 static bool is_lpss_ssp(const struct driver_data *drv_data)
188 switch (drv_data->ssp_type) {
201 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
203 return drv_data->ssp_type == QUARK_X1000_SSP;
206 static bool is_mmp2_ssp(const struct driver_data *drv_data)
208 return drv_data->ssp_type == MMP2_SSP;
211 static bool is_mrfld_ssp(const struct driver_data *drv_data)
213 return drv_data->ssp_type == MRFLD_SSP;
216 static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
218 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
219 pxa2xx_spi_write(drv_data, reg, value & mask);
222 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
224 switch (drv_data->ssp_type) {
235 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
237 switch (drv_data->ssp_type) {
247 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
251 switch (drv_data->ssp_type) {
263 return read_SSSR_bits(drv_data, mask) == mask;
266 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
271 switch (drv_data->ssp_type) {
285 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
288 switch (drv_data->ssp_type) {
301 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
304 switch (drv_data->ssp_type) {
321 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
323 WARN_ON(!drv_data->lpss_base);
324 return readl(drv_data->lpss_base + offset);
327 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
330 WARN_ON(!drv_data->lpss_base);
331 writel(value, drv_data->lpss_base + offset);
336 * @drv_data: pointer to the driver private data
341 static void lpss_ssp_setup(struct driver_data *drv_data)
346 config = lpss_get_config(drv_data);
347 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
350 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
353 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
356 if (drv_data->controller_info->enable_dma) {
357 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
360 value = __lpss_ssp_read_priv(drv_data,
363 __lpss_ssp_write_priv(drv_data,
372 struct driver_data *drv_data =
379 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
393 __lpss_ssp_write_priv(drv_data,
396 (drv_data->controller->max_speed_hz / 2));
402 struct driver_data *drv_data =
407 config = lpss_get_config(drv_data);
412 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
417 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
427 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
431 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
432 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
438 struct driver_data *drv_data =
441 if (drv_data->ssp_type == CE4100_SSP) {
442 pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0));
446 if (is_lpss_ssp(drv_data))
452 struct driver_data *drv_data =
456 if (drv_data->ssp_type == CE4100_SSP)
461 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
465 if (is_lpss_ssp(drv_data))
477 int pxa2xx_spi_flush(struct driver_data *drv_data)
482 while (read_SSSR_bits(drv_data, SSSR_RNE))
483 pxa2xx_spi_read(drv_data, SSDR);
484 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
485 write_SSSR_CS(drv_data, SSSR_ROR);
490 static void pxa2xx_spi_off(struct driver_data *drv_data)
493 if (is_mmp2_ssp(drv_data))
496 pxa_ssp_disable(drv_data->ssp);
499 static int null_writer(struct driver_data *drv_data)
501 u8 n_bytes = drv_data->n_bytes;
503 if (pxa2xx_spi_txfifo_full(drv_data)
504 || (drv_data->tx == drv_data->tx_end))
507 pxa2xx_spi_write(drv_data, SSDR, 0);
508 drv_data->tx += n_bytes;
513 static int null_reader(struct driver_data *drv_data)
515 u8 n_bytes = drv_data->n_bytes;
517 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
518 pxa2xx_spi_read(drv_data, SSDR);
519 drv_data->rx += n_bytes;
522 return drv_data->rx == drv_data->rx_end;
525 static int u8_writer(struct driver_data *drv_data)
527 if (pxa2xx_spi_txfifo_full(drv_data)
528 || (drv_data->tx == drv_data->tx_end))
531 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
532 ++drv_data->tx;
537 static int u8_reader(struct driver_data *drv_data)
539 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
540 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
541 ++drv_data->rx;
544 return drv_data->rx == drv_data->rx_end;
547 static int u16_writer(struct driver_data *drv_data)
549 if (pxa2xx_spi_txfifo_full(drv_data)
550 || (drv_data->tx == drv_data->tx_end))
553 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
554 drv_data->tx += 2;
559 static int u16_reader(struct driver_data *drv_data)
561 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
562 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
563 drv_data->rx += 2;
566 return drv_data->rx == drv_data->rx_end;
569 static int u32_writer(struct driver_data *drv_data)
571 if (pxa2xx_spi_txfifo_full(drv_data)
572 || (drv_data->tx == drv_data->tx_end))
575 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
576 drv_data->tx += 4;
581 static int u32_reader(struct driver_data *drv_data)
583 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
584 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
585 drv_data->rx += 4;
588 return drv_data->rx == drv_data->rx_end;
591 static void reset_sccr1(struct driver_data *drv_data)
593 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
596 if (drv_data->controller->cur_msg) {
597 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
603 switch (drv_data->ssp_type) {
615 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
618 static void int_stop_and_reset(struct driver_data *drv_data)
621 write_SSSR_CS(drv_data, drv_data->clear_sr);
622 reset_sccr1(drv_data);
623 if (pxa25x_ssp_comp(drv_data))
626 pxa2xx_spi_write(drv_data, SSTO, 0);
629 static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
631 int_stop_and_reset(drv_data);
632 pxa2xx_spi_flush(drv_data);
633 pxa2xx_spi_off(drv_data);
635 dev_err(drv_data->ssp->dev, "%s\n", msg);
637 drv_data->controller->cur_msg->status = err;
638 spi_finalize_current_transfer(drv_data->controller);
641 static void int_transfer_complete(struct driver_data *drv_data)
643 int_stop_and_reset(drv_data);
645 spi_finalize_current_transfer(drv_data->controller);
648 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
652 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
653 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
657 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
662 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
667 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
668 if (drv_data->read(drv_data)) {
669 int_transfer_complete(drv_data);
676 if (drv_data->read(drv_data)) {
677 int_transfer_complete(drv_data);
680 } while (drv_data->write(drv_data));
682 if (drv_data->read(drv_data)) {
683 int_transfer_complete(drv_data);
687 if (drv_data->tx == drv_data->tx_end) {
691 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
698 if (pxa25x_ssp_comp(drv_data)) {
701 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
703 bytes_left = drv_data->rx_end - drv_data->rx;
704 switch (drv_data->n_bytes) {
713 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
717 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
719 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
726 static void handle_bad_msg(struct driver_data *drv_data)
728 int_stop_and_reset(drv_data);
729 pxa2xx_spi_off(drv_data);
731 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
736 struct driver_data *drv_data = dev_id;
738 u32 mask = drv_data->mask_sr;
747 if (pm_runtime_suspended(drv_data->ssp->dev))
756 status = pxa2xx_spi_read(drv_data, SSSR);
760 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
773 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
774 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
776 if (!drv_data->controller->cur_msg) {
777 handle_bad_msg(drv_data);
782 return drv_data->transfer_handler(drv_data);
906 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
908 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
909 const struct ssp_device *ssp = drv_data->ssp;
923 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
927 spi_get_ctldata(drv_data->controller->cur_msg->spi);
930 switch (drv_data->ssp_type) {
935 clk_div = ssp_get_clk_div(drv_data, rate);
945 struct driver_data *drv_data = spi_controller_get_devdata(controller);
947 return drv_data->controller_info->enable_dma &&
949 xfer->len >= drv_data->controller_info->dma_burst_size;
956 struct driver_data *drv_data = spi_controller_get_devdata(controller);
958 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
969 if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) {
977 if (pxa2xx_spi_flush(drv_data) == 0) {
981 drv_data->tx = (void *)transfer->tx_buf;
982 drv_data->tx_end = drv_data->tx + transfer->len;
983 drv_data->rx = transfer->rx_buf;
984 drv_data->rx_end = drv_data->rx + transfer->len;
990 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
993 drv_data->n_bytes = 1;
994 drv_data->read = drv_data->rx ? u8_reader : null_reader;
995 drv_data->write = drv_data->tx ? u8_writer : null_writer;
997 drv_data->n_bytes = 2;
998 drv_data->read = drv_data->rx ? u16_reader : null_reader;
999 drv_data->write = drv_data->tx ? u16_writer : null_writer;
1001 drv_data->n_bytes = 4;
1002 drv_data->read = drv_data->rx ? u32_reader : null_reader;
1003 drv_data->write = drv_data->tx ? u32_writer : null_writer;
1013 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1015 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1020 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1021 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1023 pxa2xx_spi_dma_start(drv_data);
1026 drv_data->transfer_handler = interrupt_transfer;
1029 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1030 write_SSSR_CS(drv_data, drv_data->clear_sr);
1034 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1035 if (!pxa25x_ssp_comp(drv_data))
1046 if (is_lpss_ssp(drv_data)) {
1047 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1048 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1051 if (is_mrfld_ssp(drv_data)) {
1058 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1061 if (is_quark_x1000_ssp(drv_data))
1062 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1065 if (!is_mmp2_ssp(drv_data))
1066 pxa_ssp_disable(drv_data->ssp);
1068 if (!pxa25x_ssp_comp(drv_data))
1069 pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT);
1072 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1075 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1078 pxa_ssp_enable(drv_data->ssp);
1080 if (is_mmp2_ssp(drv_data)) {
1081 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1088 drv_data->tx += tx_level;
1093 while (drv_data->write(drv_data))
1095 if (drv_data->gpiod_ready) {
1096 gpiod_set_value(drv_data->gpiod_ready, 1);
1098 gpiod_set_value(drv_data->gpiod_ready, 0);
1106 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1113 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1115 int_error_stop(drv_data, "transfer aborted", -EINTR);
1123 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1125 int_stop_and_reset(drv_data);
1128 pxa2xx_spi_off(drv_data);
1137 if (atomic_read(&drv_data->dma_running))
1138 pxa2xx_spi_dma_stop(drv_data);
1143 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1146 pxa2xx_spi_off(drv_data);
1155 struct driver_data *drv_data =
1159 switch (drv_data->ssp_type) {
1181 config = lpss_get_config(drv_data);
1188 if (spi_controller_is_target(drv_data->controller)) {
1198 if (drv_data->ssp_type == CE4100_SSP) {
1214 if (spi_controller_is_target(drv_data->controller)) {
1221 if (is_lpss_ssp(drv_data)) {
1227 if (is_mrfld_ssp(drv_data)) {
1232 switch (drv_data->ssp_type) {
1378 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1380 if (has_acpi_companion(drv_data->ssp->dev)) {
1381 switch (drv_data->ssp_type) {
1409 struct driver_data *drv_data;
1431 controller = devm_spi_alloc_target(dev, sizeof(*drv_data));
1433 controller = devm_spi_alloc_host(dev, sizeof(*drv_data));
1439 drv_data = spi_controller_get_devdata(controller);
1440 drv_data->controller = controller;
1441 drv_data->controller_info = platform_info;
1442 drv_data->ssp = ssp;
1462 drv_data->ssp_type = ssp->type;
1464 if (pxa25x_ssp_comp(drv_data)) {
1465 switch (drv_data->ssp_type) {
1474 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1475 drv_data->dma_cr1 = 0;
1476 drv_data->clear_sr = SSSR_ROR;
1477 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1480 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1481 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1482 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1483 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1488 drv_data);
1496 status = pxa2xx_spi_dma_setup(drv_data);
1518 if (!pxa25x_ssp_comp(drv_data))
1521 else if (!is_quark_x1000_ssp(drv_data))
1528 switch (drv_data->ssp_type) {
1532 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1536 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1541 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1543 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1558 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1562 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1566 if (!pxa25x_ssp_comp(drv_data))
1567 pxa2xx_spi_write(drv_data, SSTO, 0);
1569 if (!is_quark_x1000_ssp(drv_data))
1570 pxa2xx_spi_write(drv_data, SSPSP, 0);
1572 if (is_lpss_ssp(drv_data)) {
1573 lpss_ssp_setup(drv_data);
1574 config = lpss_get_config(drv_data);
1576 tmp = __lpss_ssp_read_priv(drv_data,
1589 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1591 if (IS_ERR(drv_data->gpiod_ready)) {
1592 status = PTR_ERR(drv_data->gpiod_ready);
1603 platform_set_drvdata(pdev, drv_data);
1619 pxa2xx_spi_dma_release(drv_data);
1620 free_irq(ssp->irq, drv_data);
1629 struct driver_data *drv_data = platform_get_drvdata(pdev);
1630 struct ssp_device *ssp = drv_data->ssp;
1634 spi_unregister_controller(drv_data->controller);
1641 if (drv_data->controller_info->enable_dma)
1642 pxa2xx_spi_dma_release(drv_data);
1648 free_irq(ssp->irq, drv_data);
1656 struct driver_data *drv_data = dev_get_drvdata(dev);
1657 struct ssp_device *ssp = drv_data->ssp;
1660 status = spi_controller_suspend(drv_data->controller);
1674 struct driver_data *drv_data = dev_get_drvdata(dev);
1675 struct ssp_device *ssp = drv_data->ssp;
1686 return spi_controller_resume(drv_data->controller);
1691 struct driver_data *drv_data = dev_get_drvdata(dev);
1693 clk_disable_unprepare(drv_data->ssp->clk);
1699 struct driver_data *drv_data = dev_get_drvdata(dev);
1701 return clk_prepare_enable(drv_data->ssp->clk);