Lines Matching defs:mas
106 static void spi_slv_setup(struct spi_geni_master *mas)
108 struct geni_se *se = &mas->se;
113 dev_dbg(mas->dev, "spi slave setup done\n");
117 struct spi_geni_master *mas,
125 ret = geni_se_clk_freq_match(&mas->se,
126 speed_hz * mas->oversampling,
129 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
134 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
135 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
137 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
139 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
141 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
143 mas->cur_sclk_hz = sclk_freq;
151 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
153 struct geni_se *se = &mas->se;
156 spin_lock_irq(&mas->lock);
157 if (mas->cur_xfer_mode == GENI_SE_FIFO)
160 xfer = mas->cur_xfer;
161 mas->cur_xfer = NULL;
168 spin_unlock_irq(&mas->lock);
172 reinit_completion(&mas->cancel_done);
174 spin_unlock_irq(&mas->lock);
176 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
180 spin_lock_irq(&mas->lock);
181 reinit_completion(&mas->abort_done);
183 spin_unlock_irq(&mas->lock);
185 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
187 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
193 mas->abort_failed = true;
197 if (mas->cur_xfer_mode == GENI_SE_DMA) {
200 spin_lock_irq(&mas->lock);
201 reinit_completion(&mas->tx_reset_done);
203 spin_unlock_irq(&mas->lock);
204 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ);
206 dev_err(mas->dev, "DMA TX RESET failed\n");
209 spin_lock_irq(&mas->lock);
210 reinit_completion(&mas->rx_reset_done);
212 spin_unlock_irq(&mas->lock);
213 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ);
215 dev_err(mas->dev, "DMA RX RESET failed\n");
223 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n");
230 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
232 dmaengine_terminate_sync(mas->tx);
233 dmaengine_terminate_sync(mas->rx);
238 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
240 switch (mas->cur_xfer_mode) {
249 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode);
253 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
255 struct geni_se *se = &mas->se;
258 if (!mas->abort_failed)
267 spin_lock_irq(&mas->lock);
270 spin_unlock_irq(&mas->lock);
273 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
282 mas->abort_failed = false;
289 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
290 struct spi_controller *spi = dev_get_drvdata(mas->dev);
291 struct geni_se *se = &mas->se;
297 if (set_flag == mas->cs_flag)
300 pm_runtime_get_sync(mas->dev);
302 if (spi_geni_is_abort_still_pending(mas)) {
303 dev_err(mas->dev, "Can't set chip select\n");
307 spin_lock_irq(&mas->lock);
308 if (mas->cur_xfer) {
309 dev_err(mas->dev, "Can't set CS when prev xfer running\n");
310 spin_unlock_irq(&mas->lock);
314 mas->cs_flag = set_flag;
316 mas->cur_xfer_mode = GENI_SE_FIFO;
317 geni_se_select_mode(se, mas->cur_xfer_mode);
319 reinit_completion(&mas->cs_done);
324 spin_unlock_irq(&mas->lock);
326 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
328 dev_warn(mas->dev, "Timeout setting chip select\n");
333 pm_runtime_put(mas->dev);
336 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
341 struct geni_se *se = &mas->se;
348 if (!(mas->fifo_width_bits % bits_per_word))
349 pack_words = mas->fifo_width_bits / bits_per_word;
352 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
358 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
362 struct geni_se *se = &mas->se;
365 if (clk_hz == mas->cur_speed_hz)
368 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
370 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
381 mas->cur_speed_hz = clk_hz;
389 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
400 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
401 struct geni_se *se = &mas->se;
405 if (mas->last_mode != spi_slv->mode) {
419 mas->cur_bits_per_word = spi_slv->bits_per_word;
421 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
428 mas->last_mode = spi_slv->mode;
431 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
456 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
469 if (xfer->bits_per_word != mas->cur_bits_per_word ||
470 xfer->speed_hz != mas->cur_speed_hz) {
471 mas->cur_bits_per_word = xfer->bits_per_word;
472 mas->cur_speed_hz = xfer->speed_hz;
482 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
483 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
485 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
498 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
501 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
511 dmaengine_slave_config(mas->rx, &config);
512 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
515 dev_err(mas->dev, "Err setting up rx desc\n");
524 dmaengine_slave_config(mas->tx, &config);
525 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
528 dev_err(mas->dev, "Err setting up tx desc\n");
540 dma_async_issue_pending(mas->rx);
542 dma_async_issue_pending(mas->tx);
547 struct spi_geni_master *mas)
551 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
552 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
554 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
563 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
566 if (mas->cur_xfer_mode == GENI_GPI_DMA)
573 len = get_xfer_len_in_words(xfer, mas);
574 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
585 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
588 switch (mas->cur_xfer_mode) {
591 if (spi_geni_is_abort_still_pending(mas))
595 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
603 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
607 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
611 mas->tx = dma_request_chan(mas->dev, "tx");
612 if (IS_ERR(mas->tx)) {
613 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
618 mas->rx = dma_request_chan(mas->dev, "rx");
619 if (IS_ERR(mas->rx)) {
620 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
628 mas->rx = NULL;
629 dma_release_channel(mas->tx);
631 mas->tx = NULL;
635 static void spi_geni_release_dma_chan(struct spi_geni_master *mas)
637 if (mas->rx) {
638 dma_release_channel(mas->rx);
639 mas->rx = NULL;
642 if (mas->tx) {
643 dma_release_channel(mas->tx);
644 mas->tx = NULL;
648 static int spi_geni_init(struct spi_geni_master *mas)
650 struct spi_controller *spi = dev_get_drvdata(mas->dev);
651 struct geni_se *se = &mas->se;
656 pm_runtime_get_sync(mas->dev);
662 dev_err(mas->dev, "Invalid proto %d\n", proto);
665 spi_slv_setup(mas);
667 dev_err(mas->dev, "Invalid proto %d\n", proto);
670 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
673 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
679 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
681 mas->tx_wm = 1;
687 mas->oversampling = 2;
689 mas->oversampling = 1;
694 ret = spi_geni_grab_gpi_chan(mas);
696 mas->cur_xfer_mode = GENI_GPI_DMA;
698 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
707 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
711 mas->cur_xfer_mode = GENI_SE_FIFO;
725 pm_runtime_put(mas->dev);
729 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
736 if (mas->fifo_width_bits % mas->cur_bits_per_word)
737 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
740 return mas->fifo_width_bits / BITS_PER_BYTE;
743 static bool geni_spi_handle_tx(struct spi_geni_master *mas)
745 struct geni_se *se = &mas->se;
748 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
752 if (!mas->cur_xfer) {
757 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
758 if (mas->tx_rem_bytes < max_bytes)
759 max_bytes = mas->tx_rem_bytes;
761 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
773 mas->tx_rem_bytes -= max_bytes;
774 if (!mas->tx_rem_bytes) {
781 static void geni_spi_handle_rx(struct spi_geni_master *mas)
783 struct geni_se *se = &mas->se;
788 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
801 if (!mas->cur_xfer) {
807 if (mas->rx_rem_bytes < rx_bytes)
808 rx_bytes = mas->rx_rem_bytes;
810 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
822 mas->rx_rem_bytes -= rx_bytes;
826 struct spi_geni_master *mas,
831 struct geni_se *se = &mas->se;
846 spin_lock_irq(&mas->lock);
847 spin_unlock_irq(&mas->lock);
849 if (xfer->bits_per_word != mas->cur_bits_per_word) {
850 spi_setup_word_len(mas, mode, xfer->bits_per_word);
851 mas->cur_bits_per_word = xfer->bits_per_word;
855 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
859 mas->tx_rem_bytes = 0;
860 mas->rx_rem_bytes = 0;
862 len = get_xfer_len_in_words(xfer, mas);
864 mas->cur_xfer = xfer;
867 mas->tx_rem_bytes = xfer->len;
874 mas->rx_rem_bytes = xfer->len;
884 mas->cur_xfer_mode = GENI_SE_FIFO;
886 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n",
888 mas->cur_xfer_mode = GENI_SE_FIFO;
890 mas->cur_xfer_mode = GENI_SE_DMA;
891 geni_se_select_mode(se, mas->cur_xfer_mode);
897 spin_lock_irq(&mas->lock);
900 if (mas->cur_xfer_mode == GENI_SE_DMA) {
908 if (geni_spi_handle_tx(mas))
909 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
912 spin_unlock_irq(&mas->lock);
920 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
923 if (spi_geni_is_abort_still_pending(mas))
930 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) {
931 ret = setup_se_xfer(xfer, mas, slv->mode, spi);
937 return setup_gsi_xfer(xfer, mas, slv, spi);
943 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
944 struct geni_se *se = &mas->se;
954 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
956 spin_lock(&mas->lock);
958 if (mas->cur_xfer_mode == GENI_SE_FIFO) {
960 geni_spi_handle_rx(mas);
963 geni_spi_handle_tx(mas);
966 if (mas->cur_xfer) {
968 mas->cur_xfer = NULL;
982 if (mas->tx_rem_bytes) {
984 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
985 mas->tx_rem_bytes, mas->cur_bits_per_word);
987 if (mas->rx_rem_bytes)
988 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
989 mas->rx_rem_bytes, mas->cur_bits_per_word);
991 complete(&mas->cs_done);
994 } else if (mas->cur_xfer_mode == GENI_SE_DMA) {
995 const struct spi_transfer *xfer = mas->cur_xfer;
1004 mas->tx_rem_bytes = 0;
1006 mas->rx_rem_bytes = 0;
1008 complete(&mas->tx_reset_done);
1010 complete(&mas->rx_reset_done);
1011 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) {
1013 mas->cur_xfer = NULL;
1018 complete(&mas->cancel_done);
1020 complete(&mas->abort_done);
1037 spin_unlock(&mas->lock);
1046 struct spi_geni_master *mas;
1067 spi = devm_spi_alloc_host(dev, sizeof(*mas));
1072 mas = spi_controller_get_devdata(spi);
1073 mas->irq = irq;
1074 mas->dev = dev;
1075 mas->se.dev = dev;
1076 mas->se.wrapper = dev_get_drvdata(dev->parent);
1077 mas->se.base = base;
1078 mas->se.clk = clk;
1105 init_completion(&mas->cs_done);
1106 init_completion(&mas->cancel_done);
1107 init_completion(&mas->abort_done);
1108 init_completion(&mas->tx_reset_done);
1109 init_completion(&mas->rx_reset_done);
1110 spin_lock_init(&mas->lock);
1118 ret = geni_icc_get(&mas->se, NULL);
1122 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
1123 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1125 ret = geni_icc_set_bw(&mas->se);
1129 ret = spi_geni_init(mas);
1138 if (!spi->target && mas->cur_xfer_mode == GENI_SE_FIFO)
1144 if (mas->cur_xfer_mode == GENI_GPI_DMA)
1147 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
1157 free_irq(mas->irq, spi);
1159 spi_geni_release_dma_chan(mas);
1168 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1173 spi_geni_release_dma_chan(mas);
1175 free_irq(mas->irq, spi);
1182 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1188 ret = geni_se_resources_off(&mas->se);
1192 return geni_icc_disable(&mas->se);
1198 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1201 ret = geni_icc_enable(&mas->se);
1205 ret = geni_se_resources_on(&mas->se);
1209 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);