Lines Matching refs:cqspi
61 struct cqspi_st *cqspi;
115 u32 (*get_dma_status)(struct cqspi_st *cqspi);
117 struct cqspi_st *cqspi);
325 static bool cqspi_is_idle(struct cqspi_st *cqspi)
327 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
332 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
334 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
340 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
344 dma_status = readl(cqspi->iobase +
346 writel(dma_status, cqspi->iobase +
354 struct cqspi_st *cqspi = dev;
355 const struct cqspi_driver_platdata *ddata = cqspi->ddata;
359 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
362 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
364 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
365 if (ddata->get_dma_status(cqspi)) {
366 complete(&cqspi->transfer_complete);
371 else if (!cqspi->slow_sram)
377 complete(&cqspi->transfer_complete);
407 static int cqspi_wait_idle(struct cqspi_st *cqspi)
420 if (cqspi_is_idle(cqspi))
430 dev_err(&cqspi->pdev->dev,
440 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
442 void __iomem *reg_base = cqspi->iobase;
452 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,
455 dev_err(&cqspi->pdev->dev,
461 return cqspi_wait_idle(cqspi);
468 struct cqspi_st *cqspi = f_pdata->cqspi;
469 void __iomem *reg_base = cqspi->iobase;
490 struct cqspi_st *cqspi = f_pdata->cqspi;
491 void __iomem *reg_base = cqspi->iobase;
519 return cqspi_wait_idle(cqspi);
525 struct cqspi_st *cqspi = f_pdata->cqspi;
526 void __iomem *reg_base = cqspi->iobase;
541 dev_err(&cqspi->pdev->dev,
581 status = cqspi_exec_flash_cmd(cqspi, reg);
608 struct cqspi_st *cqspi = f_pdata->cqspi;
609 void __iomem *reg_base = cqspi->iobase;
623 dev_err(&cqspi->pdev->dev,
666 ret = cqspi_exec_flash_cmd(cqspi, reg);
677 struct cqspi_st *cqspi = f_pdata->cqspi;
678 void __iomem *reg_base = cqspi->iobase;
720 struct cqspi_st *cqspi = f_pdata->cqspi;
721 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ);
722 struct device *dev = &cqspi->pdev->dev;
723 void __iomem *reg_base = cqspi->iobase;
724 void __iomem *ahb_base = cqspi->ahb_base;
745 if (use_irq && cqspi->slow_sram)
752 reinit_completion(&cqspi->transfer_complete);
758 !wait_for_completion_timeout(&cqspi->transfer_complete,
766 if (cqspi->slow_sram)
769 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
779 bytes_to_read *= cqspi->fifo_width;
797 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
801 reinit_completion(&cqspi->transfer_complete);
802 if (cqspi->slow_sram)
808 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,
833 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
835 void __iomem *reg_base = cqspi->iobase;
852 struct cqspi_st *cqspi = f_pdata->cqspi;
853 struct device *dev = &cqspi->pdev->dev;
854 void __iomem *reg_base = cqspi->iobase;
868 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
872 cqspi_controller_enable(cqspi, 0);
874 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
876 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
878 cqspi_controller_enable(cqspi, 1);
908 writel(cqspi->trigger_address, reg_base +
921 reinit_completion(&cqspi->transfer_complete);
923 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
930 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
934 cqspi->iobase + CQSPI_REG_INDIRECTRD);
937 cqspi_controller_enable(cqspi, 0);
939 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
941 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
943 cqspi_controller_enable(cqspi, 1);
945 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
972 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
974 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
976 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
986 struct cqspi_st *cqspi = f_pdata->cqspi;
987 void __iomem *reg_base = cqspi->iobase;
1018 if (cqspi->wr_completion) {
1027 cqspi->use_direct_mode_wr = false;
1041 struct cqspi_st *cqspi = f_pdata->cqspi;
1042 struct device *dev = &cqspi->pdev->dev;
1043 void __iomem *reg_base = cqspi->iobase;
1056 reinit_completion(&cqspi->transfer_complete);
1066 if (cqspi->wr_delay)
1067 ndelay(cqspi->wr_delay);
1073 if (cqspi->apb_ahb_hazard)
1084 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1091 iowrite32(temp, cqspi->ahb_base);
1095 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1105 reinit_completion(&cqspi->transfer_complete);
1109 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,
1122 cqspi_wait_idle(cqspi);
1138 struct cqspi_st *cqspi = f_pdata->cqspi;
1139 void __iomem *reg_base = cqspi->iobase;
1144 if (cqspi->is_decoded_cs) {
1178 struct cqspi_st *cqspi = f_pdata->cqspi;
1179 void __iomem *iobase = cqspi->iobase;
1180 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1186 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1208 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1210 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1211 void __iomem *reg_base = cqspi->iobase;
1215 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1220 dev_warn(&cqspi->pdev->dev,
1222 cqspi->sclk, ref_clk_hz/((div+1)*2));
1231 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1235 void __iomem *reg_base = cqspi->iobase;
1257 struct cqspi_st *cqspi = f_pdata->cqspi;
1258 int switch_cs = (cqspi->current_cs != f_pdata->cs);
1259 int switch_ck = (cqspi->sclk != sclk);
1262 cqspi_controller_enable(cqspi, 0);
1266 cqspi->current_cs = f_pdata->cs;
1272 cqspi->sclk = sclk;
1273 cqspi_config_baudrate_div(cqspi);
1275 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1280 cqspi_controller_enable(cqspi, 1);
1286 struct cqspi_st *cqspi = f_pdata->cqspi;
1304 if (!op->cmd.dtr && cqspi->use_direct_mode &&
1305 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
1306 memcpy_toio(cqspi->ahb_base + to, buf, len);
1307 return cqspi_wait_idle(cqspi);
1315 struct cqspi_st *cqspi = param;
1317 complete(&cqspi->rx_dma_complete);
1323 struct cqspi_st *cqspi = f_pdata->cqspi;
1324 struct device *dev = &cqspi->pdev->dev;
1326 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1333 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1334 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1338 ddev = cqspi->rx_chan->device->dev;
1344 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1353 tx->callback_param = cqspi;
1355 reinit_completion(&cqspi->rx_dma_complete);
1364 dma_async_issue_pending(cqspi->rx_chan);
1365 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1367 dmaengine_terminate_sync(cqspi->rx_chan);
1382 struct cqspi_st *cqspi = f_pdata->cqspi;
1383 const struct cqspi_driver_platdata *ddata = cqspi->ddata;
1394 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1397 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1406 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1409 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
1434 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1435 struct device *dev = &cqspi->pdev->dev;
1524 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1526 struct device *dev = &cqspi->pdev->dev;
1530 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1532 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1534 cqspi->fifo_depth = 0;
1537 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1543 &cqspi->trigger_address)) {
1548 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1549 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1551 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1555 cqspi->pd_dev_id = id[1];
1560 static void cqspi_controller_init(struct cqspi_st *cqspi)
1565 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1568 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1571 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1574 writel(cqspi->trigger_address,
1575 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1578 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1579 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1581 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1582 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1585 if (!cqspi->use_direct_mode) {
1586 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1588 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1592 if (cqspi->use_dma_read) {
1593 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1595 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1599 static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi)
1601 struct device *dev = &cqspi->pdev->dev;
1608 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1609 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1613 if (cqspi->fifo_depth == 0) {
1614 cqspi->fifo_depth = fifo_depth;
1616 } else if (fifo_depth != cqspi->fifo_depth) {
1618 fifo_depth, cqspi->fifo_depth);
1622 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1629 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1630 if (IS_ERR(cqspi->rx_chan)) {
1631 int ret = PTR_ERR(cqspi->rx_chan);
1633 cqspi->rx_chan = NULL;
1634 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1636 init_completion(&cqspi->rx_dma_complete);
1643 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1644 struct device *dev = &cqspi->pdev->dev;
1660 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1662 unsigned int max_cs = cqspi->num_chipselect - 1;
1663 struct platform_device *pdev = cqspi->pdev;
1679 if (cs >= cqspi->num_chipselect) {
1687 f_pdata = &cqspi->f_pdata[cs];
1688 f_pdata->cqspi = cqspi;
1698 cqspi->num_chipselect = max_cs + 1;
1702 static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi)
1717 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;
1718 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;
1720 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
1726 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
1732 cqspi->is_jh7110 = true;
1737 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1742 static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi)
1744 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);
1745 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1754 struct cqspi_st *cqspi;
1758 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
1767 cqspi = spi_controller_get_devdata(host);
1769 cqspi->pdev = pdev;
1770 cqspi->host = host;
1771 cqspi->is_jh7110 = false;
1772 cqspi->ddata = ddata = of_device_get_match_data(dev);
1773 platform_set_drvdata(pdev, cqspi);
1776 ret = cqspi_of_get_pdata(cqspi);
1783 cqspi->clk = devm_clk_get(dev, NULL);
1784 if (IS_ERR(cqspi->clk)) {
1786 ret = PTR_ERR(cqspi->clk);
1791 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
1792 if (IS_ERR(cqspi->iobase)) {
1794 ret = PTR_ERR(cqspi->iobase);
1799 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
1800 if (IS_ERR(cqspi->ahb_base)) {
1802 ret = PTR_ERR(cqspi->ahb_base);
1805 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1806 cqspi->ahb_size = resource_size(res_ahb);
1808 init_completion(&cqspi->transfer_complete);
1820 ret = clk_prepare_enable(cqspi->clk);
1858 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1859 host->max_speed_hz = cqspi->master_ref_clk_hz;
1862 cqspi->wr_completion = true;
1866 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1867 cqspi->master_ref_clk_hz);
1871 cqspi->use_direct_mode = true;
1872 cqspi->use_direct_mode_wr = true;
1875 cqspi->use_dma_read = true;
1877 cqspi->wr_completion = false;
1879 cqspi->slow_sram = true;
1881 cqspi->apb_ahb_hazard = true;
1884 ret = cqspi_jh7110_clk_init(pdev, cqspi);
1898 pdev->name, cqspi);
1904 cqspi_wait_idle(cqspi);
1905 cqspi_controller_enable(cqspi, 0);
1906 cqspi_controller_detect_fifo_depth(cqspi);
1907 cqspi_controller_init(cqspi);
1908 cqspi_controller_enable(cqspi, 1);
1909 cqspi->current_cs = -1;
1910 cqspi->sclk = 0;
1912 ret = cqspi_setup_flash(cqspi);
1918 host->num_chipselect = cqspi->num_chipselect;
1920 if (cqspi->use_direct_mode) {
1921 ret = cqspi_request_mmap_dma(cqspi);
1928 if (cqspi->rx_chan)
1929 dma_release_channel(cqspi->rx_chan);
1948 cqspi_controller_enable(cqspi, 0);
1950 if (cqspi->is_jh7110)
1951 cqspi_jh7110_disable_clk(pdev, cqspi);
1952 clk_disable_unprepare(cqspi->clk);
1959 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1961 spi_unregister_controller(cqspi->host);
1962 cqspi_controller_enable(cqspi, 0);
1964 if (cqspi->rx_chan)
1965 dma_release_channel(cqspi->rx_chan);
1967 clk_disable_unprepare(cqspi->clk);
1969 if (cqspi->is_jh7110)
1970 cqspi_jh7110_disable_clk(pdev, cqspi);
1978 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1980 cqspi_controller_enable(cqspi, 0);
1981 clk_disable_unprepare(cqspi->clk);
1987 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1989 clk_prepare_enable(cqspi->clk);
1990 cqspi_wait_idle(cqspi);
1991 cqspi_controller_enable(cqspi, 0);
1992 cqspi_controller_init(cqspi);
1993 cqspi_controller_enable(cqspi, 1);
1995 cqspi->current_cs = -1;
1996 cqspi->sclk = 0;
2002 struct cqspi_st *cqspi = dev_get_drvdata(dev);
2004 return spi_controller_suspend(cqspi->host);
2009 struct cqspi_st *cqspi = dev_get_drvdata(dev);
2011 return spi_controller_resume(cqspi->host);