fsl/dpio/qbman-portal.c

270 	p->dqrr.next_idx = 0;
271 	p->dqrr.valid_bit = QB_VALID_BIT;
274 		p->dqrr.dqrr_size = 4;
275 		p->dqrr.reset_bug = 1;
277 		p->dqrr.dqrr_size = 8;
278 		p->dqrr.reset_bug = 0;
286 		reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
300 		reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
361 	qbman_swp_set_irq_coalescing(p, p->dqrr.dqrr_size - 1, 0);
1184 	if (unlikely(s->dqrr.reset_bug)) {
1197 		if (pi == s->dqrr.next_idx)
1208 		if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
1210 				 s->dqrr.next_idx, pi);
1211 			s->dqrr.reset_bug = 0;
1214 				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
1217 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
1228 	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
1230 				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
1237 	s->dqrr.next_idx++;
1238 	s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
1239 	if (!s->dqrr.next_idx)
1240 		s->dqrr.valid_bit ^= QB_VALID_BIT;
1253 	prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
1276 	if (unlikely(s->dqrr.reset_bug)) {
1289 		if (pi == s->dqrr.next_idx)
1300 		if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
1302 				 s->dqrr.next_idx, pi);
1303 			s->dqrr.reset_bug = 0;
1306 				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
1309 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR_MEM(s->dqrr.next_idx));
1320 	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
1322 				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
1329 	s->dqrr.next_idx++;
1330 	s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
1331 	if (!s->dqrr.next_idx)
1332 		s->dqrr.valid_bit ^= QB_VALID_BIT;
1345 	prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
1825 	if (irq_threshold >= p->dqrr.dqrr_size) {
1826 		pr_err("irq_threshold must be < %u\n", p->dqrr.dqrr_size - 1);