Lines Matching refs:ha
38 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
40 if ((off < ha->first_page_group_end) &&
41 (off >= ha->first_page_group_start))
42 return (void __iomem *)(ha->nx_pcibase + off);
359 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
363 ha->crb_win = CRB_HI(*off);
364 writel(ha->crb_win,
365 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
369 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
370 if (win_read != ha->crb_win) {
371 DEBUG2(ql4_printk(KERN_INFO, ha,
373 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
383 static int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
389 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
398 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
402 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
404 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
408 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
413 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
418 write_lock_irqsave(&ha->hw_lock, flags);
419 qla4_82xx_crb_win_lock(ha);
420 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
426 qla4_82xx_crb_win_unlock(ha);
427 write_unlock_irqrestore(&ha->hw_lock, flags);
431 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
437 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
442 write_lock_irqsave(&ha->hw_lock, flags);
443 qla4_82xx_crb_win_lock(ha);
444 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
449 qla4_82xx_crb_win_unlock(ha);
450 write_unlock_irqrestore(&ha->hw_lock, flags);
456 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
462 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
468 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
470 DEBUG2(ql4_printk(KERN_INFO, ha,
477 ha->nx_pcibase));
482 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
488 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
493 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
495 DEBUG2(ql4_printk(KERN_INFO, ha,
502 ha->nx_pcibase));
511 * @ha: pointer to adapter structure
518 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
526 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
538 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
540 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
544 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
553 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
568 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
583 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
599 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
608 ha->ddr_mn_window = window;
609 qla4_82xx_wr_32(ha, ha->mn_win_crb |
611 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
614 ql4_printk(KERN_WARNING, ha,
629 ha->ddr_mn_window = window;
630 qla4_82xx_wr_32(ha, ha->mn_win_crb |
632 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
646 ha->qdr_sn_window = window;
647 qla4_82xx_wr_32(ha, ha->ms_win_crb |
649 win_read = qla4_82xx_rd_32(ha,
650 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
673 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
695 if (ha->qdr_sn_window == window)
702 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
713 write_lock_irqsave(&ha->hw_lock, flags);
719 start = qla4_82xx_pci_set_window(ha, off);
721 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
722 write_unlock_irqrestore(&ha->hw_lock, flags);
728 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
730 write_unlock_irqrestore(&ha->hw_lock, flags);
731 mem_base = pci_resource_start(ha->pdev, 0);
747 write_lock_irqsave(&ha->hw_lock, flags);
767 write_unlock_irqrestore(&ha->hw_lock, flags);
775 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
786 write_lock_irqsave(&ha->hw_lock, flags);
792 start = qla4_82xx_pci_set_window(ha, off);
794 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
795 write_unlock_irqrestore(&ha->hw_lock, flags);
801 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
803 write_unlock_irqrestore(&ha->hw_lock, flags);
804 mem_base = pci_resource_start(ha->pdev, 0);
818 write_lock_irqsave(&ha->hw_lock, flags);
838 write_unlock_irqrestore(&ha->hw_lock, flags);
878 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
886 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
895 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
900 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
902 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
906 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
912 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
925 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
927 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
928 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
929 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
930 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
931 if (qla4_82xx_wait_rom_done(ha)) {
936 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
938 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
940 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
945 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
949 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
954 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
958 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
959 qla4_82xx_rom_unlock(ha);
968 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
982 qla4_82xx_rom_lock(ha);
985 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
986 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
987 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
988 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
989 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
990 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
993 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
995 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
997 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
999 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1001 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1003 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1006 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1007 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1010 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1013 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1014 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1015 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1016 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1017 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1018 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1021 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1022 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1023 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1024 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1025 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1029 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1031 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1033 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1035 qla4_82xx_rom_unlock(ha);
1042 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1043 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1044 ql4_printk(KERN_WARNING, ha,
1057 ql4_printk(KERN_WARNING, ha,
1063 ql4_printk(KERN_INFO, ha,
1068 ql4_printk(KERN_WARNING, ha,
1074 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1075 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1097 DEBUG2(ql4_printk(KERN_WARNING, ha,
1128 ql4_printk(KERN_WARNING, ha,
1134 qla4_82xx_wr_32(ha, off, buf[i].data);
1151 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1152 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1153 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1156 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1157 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1158 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1159 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1160 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1161 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1162 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1163 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1170 * @ha: Pointer to adapter structure
1178 int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
1192 write_lock_irqsave(&ha->hw_lock, flags);
1195 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1197 ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
1211 ret_val = ha->isp_ops->wr_reg_indirect(ha,
1215 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1218 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1221 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1224 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1228 ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
1234 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
1236 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1240 ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
1246 ret_val = ha->isp_ops->rd_reg_indirect(ha,
1250 ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
1268 write_unlock_irqrestore(&ha->hw_lock, flags);
1275 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1283 flashaddr = memaddr = ha->hw.flt_region_bootload;
1287 ha->host_no, __func__, flashaddr, image_start));
1290 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1291 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1297 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1311 read_lock(&ha->hw_lock);
1312 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1313 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1314 read_unlock(&ha->hw_lock);
1320 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1324 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1325 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1338 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1341 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1343 if (qla4_82xx_load_from_flash(ha, image_start)) {
1352 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1368 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1369 return qla4_82xx_pci_mem_read_direct(ha,
1385 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1387 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1389 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1391 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1394 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1409 temp = qla4_82xx_rd_32(ha,
1443 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1458 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1459 return qla4_82xx_pci_mem_write_direct(ha,
1474 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1510 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1512 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1514 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1516 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1518 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1521 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1525 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1527 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1530 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1537 ql4_printk(KERN_ERR, ha,
1548 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1555 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1565 pegtune_val = qla4_82xx_rd_32(ha,
1575 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1581 read_lock(&ha->hw_lock);
1582 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1583 read_unlock(&ha->hw_lock);
1588 read_lock(&ha->hw_lock);
1589 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1590 read_unlock(&ha->hw_lock);
1596 DEBUG2(ql4_printk(KERN_INFO, ha,
1605 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1609 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1616 if (is_qla8032(ha) || is_qla8042(ha))
1617 drv_active |= (1 << ha->func_num);
1619 drv_active |= (1 << (ha->func_num * 4));
1621 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1622 __func__, ha->host_no, drv_active);
1623 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1627 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1631 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1638 if (is_qla8032(ha) || is_qla8042(ha))
1639 drv_active &= ~(1 << (ha->func_num));
1641 drv_active &= ~(1 << (ha->func_num * 4));
1643 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1644 __func__, ha->host_no, drv_active);
1645 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1648 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1653 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1654 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1661 if (is_qla8032(ha) || is_qla8042(ha))
1662 rval = drv_state & (1 << ha->func_num);
1664 rval = drv_state & (1 << (ha->func_num * 4));
1666 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1672 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1676 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1683 if (is_qla8032(ha) || is_qla8042(ha))
1684 drv_state |= (1 << ha->func_num);
1686 drv_state |= (1 << (ha->func_num * 4));
1688 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1689 __func__, ha->host_no, drv_state);
1690 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1693 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1697 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1704 if (is_qla8032(ha) || is_qla8042(ha))
1705 drv_state &= ~(1 << ha->func_num);
1707 drv_state &= ~(1 << (ha->func_num * 4));
1709 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1710 __func__, ha->host_no, drv_state);
1711 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1715 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1719 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1726 if (is_qla8032(ha) || is_qla8042(ha))
1727 qsnt_state |= (1 << ha->func_num);
1729 qsnt_state |= (2 << (ha->func_num * 4));
1731 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1736 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1741 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1744 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1745 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1746 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1747 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1749 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1755 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1761 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1762 ha->link_width = (lnk >> 4) & 0x3f;
1765 return qla4_82xx_rcvpeg_ready(ha);
1768 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1778 ql4_printk(KERN_INFO, ha,
1780 rval = qla4_8xxx_get_flash_info(ha);
1784 ql4_printk(KERN_INFO, ha,
1786 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1789 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1797 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1799 if (qla4_82xx_rom_lock(ha)) {
1801 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1809 qla4_82xx_rom_unlock(ha);
1812 static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
1821 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
1826 ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
1834 static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
1842 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1847 ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
1849 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1853 ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
1861 static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
1873 ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
1877 ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
1885 static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
1892 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1896 ha->isp_ops->wr_reg_indirect(ha, addr3, value);
1897 ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
1899 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1907 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1915 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1922 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1930 static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1938 ha->fw_dump_tmplt_hdr;
1945 rval = ha->isp_ops->rd_reg_indirect(ha,
1959 static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1968 ha->fw_dump_tmplt_hdr;
1974 rval = ha->isp_ops->wr_reg_indirect(ha,
1980 rval = ha->isp_ops->wr_reg_indirect(ha,
1985 rval = ha->isp_ops->wr_reg_indirect(ha,
1993 rval = ha->isp_ops->rd_reg_indirect(ha,
2015 static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
2027 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2029 rval = qla4_83xx_check_dma_engine_state(ha);
2031 DEBUG2(ql4_printk(KERN_INFO, ha,
2038 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2042 DEBUG2(ql4_printk(KERN_INFO, ha,
2055 dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2072 dma_free_coherent(&ha->pdev->dev,
2076 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
2080 DEBUG2(ql4_printk(KERN_INFO, ha,
2092 rval = qla4_8xxx_ms_mem_write_128b(ha,
2097 ql4_printk(KERN_INFO, ha,
2103 DEBUG2(ql4_printk(KERN_INFO, ha,
2107 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
2109 DEBUG2(ql4_printk(KERN_INFO, ha,
2111 ha->host_no, rval));
2120 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2126 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
2132 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
2144 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2159 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2162 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2167 ha->isp_ops->rd_reg_indirect(ha, c_addr,
2180 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2191 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
2201 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2203 ha->fw_dump_tmplt_hdr;
2210 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2215 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2216 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2220 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2227 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2230 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2232 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2238 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2249 ha->isp_ops->rd_reg_indirect(ha,
2264 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
2286 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
2304 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2308 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
2316 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2322 DEBUG2(ql4_printk(KERN_INFO, ha,
2327 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2331 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
2336 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
2344 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2353 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2354 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2362 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
2383 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2384 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2387 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2396 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
2406 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2414 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
2417 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2429 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2438 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2443 DEBUG2(ql4_printk(KERN_INFO, ha,
2448 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2450 ha->isp_ops->rd_reg_indirect(ha,
2463 static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2473 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2478 DEBUG2(ql4_printk(KERN_INFO, ha,
2483 DEBUG2(ql4_printk(KERN_INFO, ha,
2490 DEBUG2(ql4_printk(KERN_INFO, ha,
2496 DEBUG2(ql4_printk(KERN_INFO, ha,
2500 write_lock_irqsave(&ha->hw_lock, flags);
2502 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2505 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2508 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2510 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2513 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2523 write_unlock_irqrestore(&ha->hw_lock, flags);
2528 ha->isp_ops->rd_reg_indirect(ha,
2536 write_unlock_irqrestore(&ha->hw_lock, flags);
2538 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2545 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2552 rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
2554 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2560 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2565 DEBUG2(ql4_printk(KERN_INFO, ha,
2567 ha->host_no, index, entry_hdr->entry_type,
2573 ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
2577 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2597 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2600 ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2607 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2614 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2626 static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
2654 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
2658 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2665 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2669 ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
2674 ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
2675 ha->isp_ops->wr_reg_indirect(ha, addr1, value);
2679 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2685 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2691 ha->isp_ops->wr_reg_indirect(ha, addr1,
2696 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2703 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2709 ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
2721 static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
2748 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2754 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
2760 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
2766 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
2771 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2777 rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
2796 static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
2814 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2823 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2828 ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
2829 ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
2833 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2844 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2862 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2866 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2867 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2871 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2875 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2876 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2887 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2904 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2908 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2915 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2923 ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2925 ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2926 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2930 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2937 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2953 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2965 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2968 rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2972 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2986 * @ha: pointer to adapter structure
2988 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2999 ha->fw_dump_skip_size = 0;
3000 if (!ha->fw_dump) {
3001 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
3002 __func__, ha->host_no);
3007 ha->fw_dump_tmplt_hdr;
3008 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
3009 ha->fw_dump_tmplt_size);
3010 data_collected += ha->fw_dump_tmplt_size;
3013 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
3015 ql4_printk(KERN_INFO, ha,
3018 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
3019 __func__, ha->fw_dump_capture_mask);
3020 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
3021 __func__, ha->fw_dump_size, ha->fw_dump_size);
3029 (((uint8_t *)ha->fw_dump_tmplt_hdr) +
3032 if (is_qla8032(ha) || is_qla8042(ha))
3034 tmplt_hdr->ocm_window_reg[ha->func_num];
3038 if (data_collected > ha->fw_dump_size) {
3039 ql4_printk(KERN_INFO, ha,
3041 data_collected, ha->fw_dump_size);
3046 ha->fw_dump_capture_mask)) {
3052 DEBUG2(ql4_printk(KERN_INFO, ha,
3055 (ha->fw_dump_size - data_collected)));
3062 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3065 rval = qla4_8xxx_minidump_process_control(ha,
3068 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3073 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
3077 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
3080 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3086 if (is_qla8022(ha)) {
3087 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
3089 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3090 rval = qla4_83xx_minidump_process_rdrom(ha,
3094 qla4_8xxx_mark_entry_skipped(ha,
3103 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
3106 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3114 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
3118 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
3122 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
3126 qla4_8xxx_minidump_process_queue(ha, entry_hdr,
3130 if (is_qla8022(ha)) {
3131 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3134 rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
3137 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3140 if (is_qla8022(ha)) {
3141 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3144 qla83xx_minidump_process_rdmux2(ha, entry_hdr,
3148 if (is_qla8022(ha)) {
3149 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3152 rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
3155 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3158 rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
3161 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3164 rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
3167 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3170 rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
3173 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3177 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3181 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
3189 if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
3190 ql4_printk(KERN_INFO, ha,
3192 data_collected, ha->fw_dump_size);
3197 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
3205 * @ha: pointer to adapter structure
3208 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
3216 ha->host_no);
3223 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
3226 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
3228 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
3229 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
3230 if (!qla4_8xxx_collect_md_data(ha)) {
3231 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
3232 set_bit(AF_82XX_FW_DUMPED, &ha->flags);
3234 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
3242 * @ha: pointer to adapter structure
3246 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
3253 need_reset = ha->isp_ops->need_reset(ha);
3257 if (test_bit(AF_FW_RECOVERY, &ha->flags))
3258 ha->isp_ops->rom_lock_recovery(ha);
3260 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
3263 count = qla4_8xxx_rd_direct(ha,
3270 ha->isp_ops->rom_lock_recovery(ha);
3274 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
3275 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3278 ha->isp_ops->idc_unlock(ha);
3280 if (is_qla8022(ha))
3281 qla4_8xxx_get_minidump(ha);
3283 rval = ha->isp_ops->restart_firmware(ha);
3284 ha->isp_ops->idc_lock(ha);
3287 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
3288 qla4_8xxx_clear_drv_active(ha);
3289 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3295 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
3296 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
3303 * @ha: pointer to adapter structure
3308 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
3314 ql4_printk(KERN_INFO, ha,
3317 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
3318 qla4_82xx_idc_unlock(ha);
3319 ha->isp_ops->disable_intrs(ha);
3320 qla4_82xx_idc_lock(ha);
3323 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
3324 DEBUG2(ql4_printk(KERN_INFO, ha,
3326 __func__, ha->host_no));
3327 qla4_8xxx_set_rst_ready(ha);
3329 active_mask = (~(1 << (ha->func_num * 4)));
3333 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3335 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3336 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3338 ql4_printk(KERN_INFO, ha,
3340 __func__, ha->host_no, drv_state, drv_active);
3344 ql4_printk(KERN_INFO, ha,
3354 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
3355 ql4_printk(KERN_INFO, ha,
3357 __func__, ha->host_no, drv_state,
3360 qla4_82xx_idc_unlock(ha);
3362 qla4_82xx_idc_lock(ha);
3364 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3365 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3369 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
3371 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3372 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
3377 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
3378 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3379 qla4_8xxx_set_rst_ready(ha);
3385 * @ha: pointer to adapter structure
3388 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
3390 ha->isp_ops->idc_lock(ha);
3391 qla4_8xxx_set_qsnt_ready(ha);
3392 ha->isp_ops->idc_unlock(ha);
3395 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
3400 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3401 if (drv_active == (1 << (ha->func_num * 4))) {
3402 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
3404 ql4_printk(KERN_INFO, ha,
3408 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3410 ql4_printk(KERN_INFO, ha,
3417 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
3423 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3424 if (drv_active == (1 << ha->func_num)) {
3425 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3428 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3429 ql4_printk(KERN_INFO, ha,
3433 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3436 ql4_printk(KERN_INFO, ha,
3446 idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3447 idc_ver &= ~(0x03 << (ha->func_num * 2));
3448 idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3449 qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3455 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
3460 if (test_bit(AF_INIT_DONE, &ha->flags))
3463 ha->isp_ops->idc_lock(ha);
3464 qla4_8xxx_set_drv_active(ha);
3470 if (is_qla8032(ha) || is_qla8042(ha)) {
3471 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3472 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3473 qla4_83xx_clear_idc_dontreset(ha);
3476 if (is_qla8022(ha)) {
3477 qla4_82xx_set_idc_ver(ha);
3478 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3479 rval = qla4_83xx_set_idc_ver(ha);
3481 qla4_8xxx_clear_drv_active(ha);
3484 ha->isp_ops->idc_unlock(ha);
3492 * @ha: pointer to host adapter structure.
3496 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3502 rval = qla4_8xxx_update_idc_reg(ha);
3506 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3507 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3512 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3514 ha->isp_ops->idc_lock(ha);
3518 ql4_printk(KERN_WARNING, ha,
3523 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3527 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3528 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3537 rval = qla4_8xxx_device_bootstrap(ha);
3540 ha->isp_ops->idc_unlock(ha);
3542 ha->isp_ops->idc_lock(ha);
3550 if (is_qla8032(ha) || is_qla8042(ha)) {
3551 qla4_83xx_need_reset_handler(ha);
3552 } else if (is_qla8022(ha)) {
3554 qla4_82xx_need_reset_handler(ha);
3558 (ha->nx_dev_init_timeout * HZ);
3560 ha->isp_ops->idc_unlock(ha);
3562 ha->isp_ops->idc_lock(ha);
3568 qla4_8xxx_need_qsnt_handler(ha);
3571 ha->isp_ops->idc_unlock(ha);
3573 ha->isp_ops->idc_lock(ha);
3576 ha->isp_ops->idc_unlock(ha);
3577 qla4xxx_dead_adapter_cleanup(ha);
3579 ha->isp_ops->idc_lock(ha);
3582 ha->isp_ops->idc_unlock(ha);
3583 qla4xxx_dead_adapter_cleanup(ha);
3585 ha->isp_ops->idc_lock(ha);
3590 ha->isp_ops->idc_unlock(ha);
3595 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3600 if (is_qla8032(ha) || is_qla8042(ha)) {
3601 writel(0, &ha->qla4_83xx_reg->risc_intr);
3602 readl(&ha->qla4_83xx_reg->risc_intr);
3603 } else if (is_qla8022(ha)) {
3604 writel(0, &ha->qla4_82xx_reg->host_int);
3605 readl(&ha->qla4_82xx_reg->host_int);
3608 retval = qla4_8xxx_device_state_handler(ha);
3612 qla4xxx_init_rings(ha);
3614 if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
3615 retval = qla4xxx_request_irqs(ha);
3638 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
3644 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
3650 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3656 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
3657 ql4_printk(KERN_WARNING, ha,
3665 qla4_82xx_rom_unlock(ha);
3673 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
3676 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
3681 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3693 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3698 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3706 struct ql82xx_hw_data *hw = &ha->hw;
3709 wptr = (uint16_t *)ha->request_ring;
3710 flt = (struct qla_flt_header *)ha->request_ring;
3713 if (is_qla8022(ha)) {
3714 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3716 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3717 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3718 (uint8_t *)ha->request_ring,
3727 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3738 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3751 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3798 DEBUG2(ql4_printk(KERN_INFO, ha,
3808 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
3819 struct ql82xx_hw_data *hw = &ha->hw;
3824 wptr = (uint16_t *)ha->request_ring;
3825 fdt = (struct qla_fdt_layout *)ha->request_ring;
3826 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3841 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3867 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3875 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
3880 if (!is_qla8022(ha))
3882 wptr = (uint32_t *)ha->request_ring;
3883 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3887 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3888 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3890 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3891 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3894 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3895 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3896 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3897 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3901 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3908 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3911 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3912 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3913 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3914 readl(&ha->qla4_82xx_reg->hint);
3917 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3921 intr_status = readl(&ha->qla4_82xx_reg->host_int);
3923 ha->mbox_status_count = out_count;
3924 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3925 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3927 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3928 (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled))
3929 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3935 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3940 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3944 qla4_8xxx_get_flt_info(ha, flt_addr);
3945 if (is_qla8022(ha)) {
3946 qla4_82xx_get_fdt_info(ha);
3947 qla4_82xx_get_idc_param(ha);
3948 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3949 qla4_83xx_get_idc_param(ha);
3957 * @ha: pointer to host adapter structure.
3965 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3975 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3978 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3985 * @ha: pointer to host adapter structure.
3988 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
3993 qla4_82xx_idc_lock(ha);
3994 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3997 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3998 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4000 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
4002 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
4004 qla4_82xx_idc_unlock(ha);
4006 rval = qla4_8xxx_device_state_handler(ha);
4008 qla4_82xx_idc_lock(ha);
4009 qla4_8xxx_clear_rst_ready(ha);
4010 qla4_82xx_idc_unlock(ha);
4013 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
4014 clear_bit(AF_FW_RECOVERY, &ha->flags);
4022 * @ha: pointer to host adapter structure.
4025 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
4033 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
4037 ha->host_no, __func__));
4049 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
4052 ha->host_no, __func__));
4057 if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
4060 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
4065 ha->port_num = sys_info->port_num;
4066 memcpy(ha->my_mac, &sys_info->mac_addr[0],
4067 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
4068 memcpy(ha->serial_number, &sys_info->serial_number,
4069 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
4070 memcpy(ha->model_name, &sys_info->board_id_str,
4071 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
4072 ha->phy_port_cnt = sys_info->phys_port_cnt;
4073 ha->phy_port_num = sys_info->port_num;
4074 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
4077 ha->host_no, __func__, ha->my_mac, ha->serial_number));
4082 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
4089 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
4094 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4100 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4102 DEBUG2(ql4_printk(KERN_INFO, ha,
4110 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
4115 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4121 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4123 DEBUG2(ql4_printk(KERN_INFO, ha,
4133 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
4135 qla4_8xxx_intr_enable(ha);
4137 spin_lock_irq(&ha->hardware_lock);
4139 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
4140 spin_unlock_irq(&ha->hardware_lock);
4141 set_bit(AF_INTERRUPTS_ON, &ha->flags);
4145 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
4147 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
4148 qla4_8xxx_intr_disable(ha);
4150 spin_lock_irq(&ha->hardware_lock);
4152 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
4153 spin_unlock_irq(&ha->hardware_lock);
4157 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
4161 ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES,
4164 ql4_printk(KERN_WARNING, ha,
4170 ret = request_irq(pci_irq_vector(ha->pdev, 0),
4172 ha);
4176 ret = request_irq(pci_irq_vector(ha->pdev, 1),
4177 qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha);
4184 free_irq(pci_irq_vector(ha->pdev, 0), ha);
4186 pci_free_irq_vectors(ha->pdev);
4190 int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
4195 if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
4196 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
4205 qla4xxx_free_irqs(ha);