scsi/qla2xxx/qla_nx.c

349 const char *qdev_state(uint32_t dev_state)
351 	return (dev_state < MAX_STATES) ? q_dev_state[dev_state] : "Unknown";
2879 	uint32_t dev_state, drv_state, drv_active;
2928 	dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2930 	if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2951 	uint32_t dev_state;
2956 		dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2958 	} while (dev_state == curr_state);
2960 	return dev_state;
3002 	uint32_t dev_state, drv_state, drv_active;
3033 	dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3037 	    "dev_state: 0x%08x, active_mask: 0x%08x\n",
3038 	    drv_state, drv_active, dev_state, active_mask);
3041 	    dev_state != QLA8XXX_DEV_INITIALIZING) {
3054 		dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3059 	    "dev_state: 0x%08x, active_mask: 0x%08x\n",
3060 	    drv_state, drv_active, dev_state, active_mask);
3064 	    dev_state, qdev_state(dev_state));
3067 	if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3068 	    dev_state != QLA8XXX_DEV_COLD) {
3170 	uint32_t dev_state;
3183 	dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3184 	old_dev_state = dev_state;
3187 	    dev_state, qdev_state(dev_state));
3200 		dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3201 		if (old_dev_state != dev_state) {
3203 			old_dev_state = dev_state;
3208 			    dev_state, qdev_state(dev_state));
3211 		switch (dev_state) {
3320 	uint32_t dev_state, halt_status;
3325 		dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3330 		} else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3335 		} else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3340 		} else if (dev_state == QLA8XXX_DEV_FAILED &&
3416 	uint32_t dev_state = 0;
3419 		dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3421 		dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3423 	if (dev_state == QLA8XXX_DEV_READY) {
3438 		    dev_state, qdev_state(dev_state));