Lines Matching defs:r_addr
3793 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3798 r_addr = ocm_hdr->read_addr;
3803 r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
3805 r_addr += r_stride;
3815 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3820 r_addr = mux_hdr->read_addr;
3828 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3841 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3846 r_addr = crb_hdr->addr;
3851 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3852 *data_ptr++ = cpu_to_le32(r_addr);
3854 r_addr += r_stride;
3864 uint32_t addr, r_addr, c_addr, t_r_addr;
3874 r_addr = cache_hdr->read_addr;
3906 addr = r_addr;
3923 uint32_t addr, r_addr, c_addr, t_r_addr;
3931 r_addr = cache_hdr->read_addr;
3942 addr = r_addr;
3958 uint32_t s_addr, r_addr;
3972 r_addr = q_hdr->read_addr;
3974 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3976 r_addr += r_stride;
3988 uint32_t r_addr, r_value;
3994 r_addr = rom_hdr->read_addr;
3999 (r_addr & 0xFFFF0000), 1);
4002 (r_addr & 0x0000FFFF), 0, 0);
4004 r_addr += sizeof(uint32_t);
4014 uint32_t r_addr, r_value, r_data;
4022 r_addr = m_hdr->read_addr;
4025 if (r_addr & 0xf) {
4027 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4040 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4044 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4071 r_addr += 16;