Lines Matching defs:reply
240 * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
244 * @reply: reply message frame(lower 32bit addr)
248 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
254 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
261 writel(reply, reply_free_iomem);
674 mpi_reply = ioc->scsih_cmds.reply;
983 * @mpi_reply: reply mf payload returned from firmware
1220 * @mpi_reply: reply mf payload returned from firmware
1388 * _base_display_reply_info - handle reply descriptors depending on IOC Status
1392 * @reply: reply message frame (lower 32bit addr)
1396 u32 reply)
1402 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1432 * @reply: reply message frame(lower 32bit addr)
1440 u32 reply)
1444 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1454 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1466 * @reply: reply message frame(lower 32bit addr)
1473 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1480 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1519 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1522 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1679 * _base_process_reply_queue - Process reply descriptors from reply
1681 * @reply_q: per IRQ's reply queue object.
1683 * Return: number of reply descriptors processed from reply
1694 u32 reply;
1717 reply = 0;
1735 reply = le32_to_cpu(
1737 if (reply > ioc->reply_dma_max_address ||
1738 reply < ioc->reply_dma_min_address)
1739 reply = 0;
1745 msix_index, reply);
1746 if (reply)
1748 smid, msix_index, reply);
1754 _base_async_event(ioc, msix_index, reply);
1757 /* reply free queue handling */
1758 if (reply) {
1764 cpu_to_le32(reply);
1767 reply,
1783 /* Update the reply post host index after continuously
1786 * Descriptors in the reply descriptor post queue.
1831 * For those HBA's which support combined reply queue feature
1835 * 2. Then update this register with new reply host index value
1842 * new reply host index value in ReplyPostIndex Field and msix_index
1910 * Return: number of reply descriptors processed
1932 * reply descriptor post queue in case the HBA
1933 * Firmware has posted some reply descriptors
1969 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1984 * @poll: poll over reply descriptor pools incase interrupt for
3350 * msix_vectors is always within a range of FW supported reply queue.
3410 * Enable msix_load_balance only if combined reply queue mode is
3448 * Add high iops queues count to reply queue count if high iops queues
3456 * Adjust the reply queue count incase reply queue count
3463 * Add io uring poll queues count to reply queues count
3475 * Starting index of io uring poll queues in reply queue list.
3487 * Adjust the reply queue count if the allocated
3692 /* Use the Combined reply queue feature only for SAS3 C0 & higher
3693 * revision HBAs and also only when reply queue count is greater than 8
3826 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3828 * @phys_addr: lower 32 physical addr of the reply
3837 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3845 * Return: msix index of general reply queues,
3846 * i.e. reply queue on which IO request's reply
3875 * Return: msix index of high iops reply queues.
3876 * i.e. high iops reply queue on which IO request's
3877 * reply should be posted by the HBA firmware.
3885 * reply queues in terms of batch count 16 when outstanding
4720 memcpy(&mpi_reply, ioc->base_cmds.reply,
4984 "%d reply queues\n",
4988 * enabled for all reply descriptor post queues.
4990 * enable/disable interrupt coalescing on per reply
4992 * interrupt coalescing only on first reply descriptor
5006 * Enable interrupt coalescing on all reply queues
5019 * Enable interrupt coalescing on all reply queues.
5789 if (ioc->reply) {
5790 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
5794 ioc->reply));
5795 ioc->reply = NULL;
5886 * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
5888 * @start_address: Base address of a reply queue set
5891 * Return: 1 if reply queues in a set have a same upper 32bits in their base
6070 * for reply pool.
6078 /* reply pool, 4 byte align */
6079 ioc->reply_dma_pool = dma_pool_create("reply pool",
6083 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
6085 if (!ioc->reply)
6090 ioc->reply, (unsigned long long) ioc->reply_dma));
6097 "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n",
6098 ioc->reply, (unsigned long long)ioc->reply_dma,
6105 * for reply free dma pool.
6113 /* reply free queue, 16 byte align */
6141 * for reply post free array.
6174 * for reply queues.
6193 * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
6194 * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
6195 * be within 4GB boundary i.e reply queues in a set must have same
6197 * the DMA'able memory for reply queues according.
6342 /* reply frame size */
6386 /* reply free queue sizing - taking into account for 64 FW events */
6393 /* calculate reply descriptor post queue depth */
6396 /* align the reply post queue on the next 16 count boundary */
6420 /* reply post queue, 16 byte align */
6616 /* reply pool, 4 byte align */
6625 /* reply free queue, 16 byte align */
7014 * @reply_bytes: reply length
7015 * @reply: pointer to reply payload
7022 u32 *request, int reply_bytes, u16 *reply, int timeout)
7024 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
7071 /* now wait for the reply */
7078 /* read the first two 16-bits, it gives the total length of the reply */
7079 reply[0] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell)
7087 reply[1] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell)
7100 reply[i] = le16_to_cpu(
7115 mfp = (__le32 *)reply;
7127 * @mpi_reply: the reply payload from FW
7192 memcpy(mpi_reply, ioc->base_cmds.reply,
7212 * @mpi_reply: the reply payload from FW
7267 memcpy(mpi_reply, ioc->base_cmds.reply,
7285 * _base_get_port_facts - obtain port facts reply and save in ioc
7389 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
7485 ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
7600 * @reply: reply message frame(lower 32bit addr)
7607 u32 reply)
7615 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
7625 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
7693 mpi_reply = ioc->port_enable_cmds.reply;
7709 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
8237 /* initialize reply queues */
8281 /* initialize reply free host index */
8285 /* initialize reply post host index */
8551 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8555 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8559 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8564 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8569 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8574 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8579 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8584 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
8585 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
8586 !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
8587 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
8651 kfree(ioc->tm_cmds.reply);
8652 kfree(ioc->transport_cmds.reply);
8653 kfree(ioc->scsih_cmds.reply);
8654 kfree(ioc->config_cmds.reply);
8655 kfree(ioc->base_cmds.reply);
8656 kfree(ioc->port_enable_cmds.reply);
8657 kfree(ioc->ctl_cmds.reply);
8660 ioc->ctl_cmds.reply = NULL;
8661 ioc->base_cmds.reply = NULL;
8662 ioc->tm_cmds.reply = NULL;
8663 ioc->scsih_cmds.reply = NULL;
8664 ioc->transport_cmds.reply = NULL;
8665 ioc->config_cmds.reply = NULL;
8693 kfree(ioc->ctl_cmds.reply);
8695 kfree(ioc->base_cmds.reply);
8696 kfree(ioc->port_enable_cmds.reply);
8697 kfree(ioc->tm_cmds.reply);
8698 kfree(ioc->transport_cmds.reply);
8699 kfree(ioc->scsih_cmds.reply);
8700 kfree(ioc->config_cmds.reply);