Lines Matching defs:ha
279 static void ips_free_flash_copperhead(ips_ha_t * ha);
330 static int ips_abort_init(ips_ha_t * ha, int index);
336 static int ips_poll_for_flush_complete(ips_ha_t * ha);
337 static void ips_flush_and_reset(ips_ha_t *ha);
582 ips_setup_funclist(ips_ha_t * ha)
588 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
590 ha->func.isintr = ips_isintr_morpheus;
591 ha->func.isinit = ips_isinit_morpheus;
592 ha->func.issue = ips_issue_i2o_memio;
593 ha->func.init = ips_init_morpheus;
594 ha->func.statupd = ips_statupd_morpheus;
595 ha->func.reset = ips_reset_morpheus;
596 ha->func.intr = ips_intr_morpheus;
597 ha->func.enableint = ips_enable_int_morpheus;
598 } else if (IPS_USE_MEMIO(ha)) {
600 ha->func.isintr = ips_isintr_copperhead_memio;
601 ha->func.isinit = ips_isinit_copperhead_memio;
602 ha->func.init = ips_init_copperhead_memio;
603 ha->func.statupd = ips_statupd_copperhead_memio;
604 ha->func.statinit = ips_statinit_memio;
605 ha->func.reset = ips_reset_copperhead_memio;
606 ha->func.intr = ips_intr_copperhead;
607 ha->func.erasebios = ips_erase_bios_memio;
608 ha->func.programbios = ips_program_bios_memio;
609 ha->func.verifybios = ips_verify_bios_memio;
610 ha->func.enableint = ips_enable_int_copperhead_memio;
611 if (IPS_USE_I2O_DELIVER(ha))
612 ha->func.issue = ips_issue_i2o_memio;
614 ha->func.issue = ips_issue_copperhead_memio;
617 ha->func.isintr = ips_isintr_copperhead;
618 ha->func.isinit = ips_isinit_copperhead;
619 ha->func.init = ips_init_copperhead;
620 ha->func.statupd = ips_statupd_copperhead;
621 ha->func.statinit = ips_statinit;
622 ha->func.reset = ips_reset_copperhead;
623 ha->func.intr = ips_intr_copperhead;
624 ha->func.erasebios = ips_erase_bios;
625 ha->func.programbios = ips_program_bios;
626 ha->func.verifybios = ips_verify_bios;
627 ha->func.enableint = ips_enable_int_copperhead;
629 if (IPS_USE_I2O_DELIVER(ha))
630 ha->func.issue = ips_issue_i2o;
632 ha->func.issue = ips_issue_copperhead;
648 ips_ha_t *ha;
663 ha = IPS_HA(sh);
665 if (!ha)
669 scb = &ha->scbs[ha->max_cmds - 1];
671 ips_init_scb(ha, scb);
677 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
684 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
687 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
688 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
690 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
696 ips_free(ha);
699 free_irq(ha->pcidev->irq, ha);
719 ips_ha_t *ha;
727 ha = (ips_ha_t *) ips_ha[i];
729 if (!ha)
732 if (!ha->active)
736 scb = &ha->scbs[ha->max_cmds - 1];
738 ips_init_scb(ha, scb);
744 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
751 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
754 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
756 IPS_PRINTK(KERN_WARNING, ha->pcidev,
759 IPS_PRINTK(KERN_WARNING, ha->pcidev,
777 ips_ha_t *ha;
788 ha = (ips_ha_t *) SC->device->host->hostdata;
790 if (!ha)
793 if (!ha->active)
799 item = ha->copp_waitlist.head;
805 ips_removeq_copp(&ha->copp_waitlist, item);
809 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
836 ips_ha_t *ha;
851 ha = (ips_ha_t *) SC->device->host->hostdata;
853 if (!ha) {
854 DEBUG(1, "Reset called with NULL ha struct");
859 if (!ha->active)
872 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
873 scb = &ha->scbs[ha->max_cmds - 1];
875 ips_init_scb(ha, scb);
881 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
889 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
891 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
900 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
906 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
907 ret = (*ha->func.reset) (ha);
912 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
917 ips_name, ha->host_num);
919 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
922 ips_freescb(ha, scb);
927 ips_name, ha->host_num);
929 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
934 ha->active = false;
938 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
941 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
946 ips_name, ha->host_num);
948 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
951 ips_freescb(ha, scb);
956 ips_name, ha->host_num);
958 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
963 ha->active = false;
968 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
969 ha->last_ffdc = ktime_get_real_seconds();
970 ha->reset_count++;
971 ips_ffdc_reset(ha, IPS_INTR_IORL);
975 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
977 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
980 ips_freescb(ha, scb);
984 for (i = 1; i < ha->nbus; i++)
985 ha->dcdb_active[i - 1] = 0;
988 ha->num_ioctl = 0;
990 ips_next(ha, IPS_INTR_IORL);
1023 ips_ha_t *ha;
1028 ha = (ips_ha_t *) SC->device->host->hostdata;
1030 if (!ha)
1033 if (!ha->active)
1037 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1043 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1052 ha->host_num,
1058 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1075 if (ha->scb_activelist.count != 0) {
1080 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1100 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1102 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1105 ips_next(ha, IPS_INTR_IORL);
1129 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1136 if (!ha)
1140 if (!ha->active)
1143 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1147 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1179 ips_ha_t *ha;
1182 ha = IPS_HA(SDptr->host);
1184 min = ha->max_cmds / 2;
1185 if (ha->enq->ucLogDriveCount <= 2)
1186 min = ha->max_cmds - 1;
1207 ips_ha_t *ha;
1213 ha = (ips_ha_t *) dev_id;
1214 if (!ha)
1216 host = ips_sh[ha->host_num];
1219 (*ha->func.intr) (ha);
1225 if (!ha->active) {
1230 irqstatus = (*ha->func.intr) (ha);
1235 ips_next(ha, IPS_INTR_ON);
1251 ips_intr_copperhead(ips_ha_t * ha)
1260 if (!ha)
1263 if (!ha->active)
1266 intrstatus = (*ha->func.isintr) (ha);
1277 sp = &ha->sp;
1279 intrstatus = (*ha->func.isintr) (ha);
1284 cstatus.value = (*ha->func.statupd) (ha);
1291 ips_chkstatus(ha, &cstatus);
1298 (*scb->callback) (ha, scb);
1315 ips_intr_morpheus(ips_ha_t * ha)
1324 if (!ha)
1327 if (!ha->active)
1330 intrstatus = (*ha->func.isintr) (ha);
1341 sp = &ha->sp;
1343 intrstatus = (*ha->func.isintr) (ha);
1348 cstatus.value = (*ha->func.statupd) (ha);
1355 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1361 ips_chkstatus(ha, &cstatus);
1368 (*scb->callback) (ha, scb);
1387 ips_ha_t *ha;
1391 ha = IPS_HA(SH);
1393 if (!ha)
1402 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1404 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1415 ips_ha_t *ha = NULL;
1421 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1427 if (!ha)
1437 ips_ha_t *ha = NULL;
1443 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1449 if (!ha)
1452 return ips_host_info(ha, m);
1508 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1513 if (ha->ioctl_data && length <= ha->ioctl_len)
1516 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr,
1520 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
1521 ha->ioctl_data, ha->ioctl_busaddr);
1523 ha->ioctl_data = (char *) bigger_buf;
1524 ha->ioctl_len = length;
1525 ha->ioctl_busaddr = dma_busaddr;
1542 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1557 ips_name, ha->host_num);
1560 if (ips_alloc_passthru_buffer(ha, length)) {
1561 /* allocation failure! If ha->ioctl_data exists, use it to return
1563 if (ha->ioctl_data) {
1564 pt = (ips_passthru_t *) ha->ioctl_data;
1572 ha->ioctl_datasize = length;
1574 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1575 pt = (ips_passthru_t *) ha->ioctl_data;
1589 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1591 ips_scmd_buf_write(SC, ha->ioctl_data,
1604 ips_name, ha->host_num);
1609 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1612 ret = ips_flash_copperhead(ha, pt, scb);
1613 ips_scmd_buf_write(SC, ha->ioctl_data,
1617 if (ips_usrcmd(ha, pt, scb))
1636 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1642 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1643 if (ips_usrcmd(ha, pt, scb))
1656 return ips_flash_bios(ha, pt, scb);
1659 ha->flash_data = ips_FlashData;
1660 ha->flash_busaddr = ips_flashbusaddr;
1661 ha->flash_len = PAGE_SIZE << 7;
1662 ha->flash_datasize = 0;
1663 } else if (!ha->flash_data) {
1666 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev,
1667 datasize, &ha->flash_busaddr, GFP_KERNEL);
1668 if (!ha->flash_data){
1672 ha->flash_datasize = 0;
1673 ha->flash_len = datasize;
1677 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1678 ha->flash_len) {
1679 ips_free_flash_copperhead(ha);
1680 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1685 if (!ha->flash_data)
1688 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1690 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1694 return ips_flash_bios(ha, pt, scb);
1696 return ips_flash_firmware(ha, pt, scb);
1707 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1712 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1713 (!ha->func.verifybios))
1715 if ((*ha->func.erasebios) (ha)) {
1718 ips_name, ha->host_num);
1721 if ((*ha->func.programbios) (ha,
1722 ha->flash_data +
1724 ha->flash_datasize -
1728 ips_name, ha->host_num);
1731 if ((*ha->func.verifybios) (ha,
1732 ha->flash_data +
1734 ha->flash_datasize -
1738 ips_name, ha->host_num);
1741 ips_free_flash_copperhead(ha);
1745 if (!ha->func.erasebios)
1747 if ((*ha->func.erasebios) (ha)) {
1750 ips_name, ha->host_num);
1758 ips_free_flash_copperhead(ha);
1771 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1777 if ((scb->data_len + e_len) > ha->max_xfer) {
1778 e_len = ha->max_xfer - scb->data_len;
1786 if (IPS_USE_ENH_SGLIST(ha)) {
1809 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1818 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1822 ips_free_flash_copperhead(ha);
1843 scb->data_len = ha->flash_datasize;
1845 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len,
1848 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1862 ips_free_flash_copperhead(ips_ha_t * ha)
1864 if (ha->flash_data == ips_FlashData)
1866 else if (ha->flash_data)
1867 dma_free_coherent(&ha->pcidev->dev, ha->flash_len,
1868 ha->flash_data, ha->flash_busaddr);
1869 ha->flash_data = NULL;
1882 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1889 if ((!scb) || (!pt) || (!ha))
1911 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1921 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1970 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1978 ips_name, ha->host_num);
1982 pt = (ips_passthru_t *) ha->ioctl_data;
1990 pt->AdapterType = ha->ad_type;
1992 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1995 ips_free_flash_copperhead(ha);
1997 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2010 ips_host_info(ips_ha_t *ha, struct seq_file *m)
2016 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2017 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2019 ips_adapter_name[ha->ad_type - 1]);
2023 if (ha->io_addr)
2026 ha->io_addr, ha->io_len);
2028 if (ha->mem_addr) {
2031 ha->mem_addr, ha->mem_len);
2034 (unsigned long)ha->mem_ptr);
2037 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2042 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2043 if (ha->nvram->bios_low[3] == 0) {
2046 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2047 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2048 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2049 ha->nvram->bios_low[2]);
2054 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2055 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2056 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2057 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2062 if (ha->enq->CodeBlkVersion[7] == 0) {
2065 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2066 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2067 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2068 ha->enq->CodeBlkVersion[6]);
2072 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2073 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2074 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2075 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2078 if (ha->enq->BootBlkVersion[7] == 0) {
2081 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2082 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2083 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2084 ha->enq->BootBlkVersion[6]);
2088 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2089 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2090 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2091 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2101 ha->enq->ucMaxPhysicalDevices);
2103 ha->max_cmds);
2105 ha->scb_waitlist.count);
2107 ha->scb_activelist.count - ha->num_ioctl);
2109 ha->copp_waitlist.count);
2111 ha->num_ioctl);
2128 ips_identify_controller(ips_ha_t * ha)
2132 switch (ha->pcidev->device) {
2134 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2135 ha->ad_type = IPS_ADTYPE_SERVERAID;
2136 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2137 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2138 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2139 ha->ad_type = IPS_ADTYPE_NAVAJO;
2140 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2141 && (ha->slot_num == 0)) {
2142 ha->ad_type = IPS_ADTYPE_KIOWA;
2143 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2144 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2145 if (ha->enq->ucMaxPhysicalDevices == 15)
2146 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2148 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2149 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2150 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2151 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2156 switch (ha->pcidev->subsystem_device) {
2158 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2162 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2166 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2170 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2174 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2178 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2185 switch (ha->pcidev->subsystem_device) {
2187 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2190 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2193 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2196 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2213 ips_get_bios_version(ips_ha_t * ha, int intr)
2227 memcpy(ha->bios_version, " ?", 8);
2229 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2230 if (IPS_USE_MEMIO(ha)) {
2234 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2235 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2238 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2241 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2242 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2245 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2249 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2250 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2253 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2256 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2257 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2259 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2262 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2263 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2265 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2271 outl(0, ha->io_addr + IPS_REG_FLAP);
2272 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2275 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2278 outl(1, ha->io_addr + IPS_REG_FLAP);
2279 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2282 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2286 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2287 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2290 major = inb(ha->io_addr + IPS_REG_FLDP);
2293 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2294 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2297 minor = inb(ha->io_addr + IPS_REG_FLDP);
2300 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2301 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2304 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2310 buffer = ha->ioctl_data;
2314 scb = &ha->scbs[ha->max_cmds - 1];
2316 ips_init_scb(ha, scb);
2322 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2329 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2333 ips_send_wait(ha, scb, ips_cmd_timeout,
2351 ha->bios_version[0] = hex_asc_upper_hi(major);
2352 ha->bios_version[1] = '.';
2353 ha->bios_version[2] = hex_asc_upper_lo(major);
2354 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2355 ha->bios_version[4] = '.';
2356 ha->bios_version[5] = hex_asc_upper_hi(minor);
2357 ha->bios_version[6] = hex_asc_upper_lo(minor);
2358 ha->bios_version[7] = 0;
2373 ips_hainit(ips_ha_t * ha)
2379 if (!ha)
2382 if (ha->func.statinit)
2383 (*ha->func.statinit) (ha);
2385 if (ha->func.enableint)
2386 (*ha->func.enableint) (ha);
2389 ha->reset_count = 1;
2390 ha->last_ffdc = ktime_get_real_seconds();
2391 ips_ffdc_reset(ha, IPS_INTR_IORL);
2393 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2394 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2400 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2401 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2408 ips_identify_controller(ha);
2410 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2411 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2418 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2419 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2426 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2427 ips_clear_adapter(ha, IPS_INTR_IORL);
2430 ha->ntargets = IPS_MAX_TARGETS + 1;
2431 ha->nlun = 1;
2432 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2434 switch (ha->conf->logical_drive[0].ucStripeSize) {
2436 ha->max_xfer = 0x10000;
2440 ha->max_xfer = 0x20000;
2444 ha->max_xfer = 0x40000;
2449 ha->max_xfer = 0x80000;
2454 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2456 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2459 switch (ha->conf->logical_drive[0].ucStripeSize) {
2461 ha->max_cmds = 32;
2465 ha->max_cmds = 16;
2469 ha->max_cmds = 8;
2474 ha->max_cmds = 4;
2480 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2481 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2482 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2483 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2484 ha->max_cmds = MaxLiteCmds;
2488 ha->ha_id[0] = IPS_ADAPTER_ID;
2489 for (i = 1; i < ha->nbus; i++) {
2490 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2491 ha->dcdb_active[i - 1] = 0;
2507 ips_next(ips_ha_t * ha, int intr)
2518 if (!ha)
2520 host = ips_sh[ha->host_num];
2528 if ((ha->subsys->param[3] & 0x300000)
2529 && (ha->scb_activelist.count == 0)) {
2531 if (now - ha->last_ffdc > IPS_SECS_8HOURS) {
2532 ha->last_ffdc = now;
2533 ips_ffdc_time(ha);
2544 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2545 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2547 item = ips_removeq_copp_head(&ha->copp_waitlist);
2548 ha->num_ioctl++;
2554 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2565 ips_freescb(ha, scb);
2573 ips_freescb(ha, scb);
2580 ha->num_ioctl--;
2584 ret = ips_send_cmd(ha, scb);
2587 ips_putq_scb_head(&ha->scb_activelist, scb);
2589 ha->num_ioctl--;
2597 ips_freescb(ha, scb);
2600 ips_freescb(ha, scb);
2612 p = ha->scb_waitlist.head;
2613 while ((p) && (scb = ips_getscb(ha))) {
2615 && (ha->
2618 ips_freescb(ha, scb);
2624 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2655 (ha, sg_dma_address(sg), scb, i,
2686 ret = ips_send_cmd(ha, scb);
2690 ips_putq_scb_head(&ha->scb_activelist, scb);
2699 ha->dcdb_active[scb->bus - 1] &=
2702 ips_freescb(ha, scb);
2709 ha->dcdb_active[scb->bus - 1] &=
2712 ips_freescb(ha, scb);
3069 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3073 ips_freescb(ha, scb);
3074 if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0]) {
3075 ha->waitflag = false;
3091 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3096 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3104 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3110 ips_done(ha, scb);
3123 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3133 ips_cleanup_passthru(ha, scb);
3134 ha->num_ioctl--;
3156 ips_fill_scb_sg_single(ha,
3164 (ha,
3183 ret = ips_send_cmd(ha, scb);
3192 ips_freescb(ha, scb);
3200 ips_freescb(ha, scb);
3211 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3216 ips_freescb(ha, scb);
3229 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3242 ips_name, ha->host_num,
3368 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3375 ha->waitflag = true;
3376 ha->cmd_in_progress = scb->cdb[0];
3379 ret = ips_send_cmd(ha, scb);
3385 ret = ips_wait(ha, timeout, intr);
3434 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3452 if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0])
3453 ha->waitflag = false;
3518 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3522 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3531 ips_reqsen(ha, scb);
3550 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3556 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3596 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3602 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3641 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3644 scb->data_len = sizeof (*ha->enq);
3645 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3651 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3656 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3699 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3704 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3705 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3718 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3725 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3764 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3802 return ((*ha->func.issue) (ha, scb));
3815 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3826 scb = &ha->scbs[pstatus->fields.command_id];
3831 sp = &ha->sp;
3836 ips_removeq_scb(&ha->scb_activelist, scb);
3844 ha->host_num,
3863 ips_name, ha->host_num,
3881 if (!ips_online(ha, scb)) {
3887 if (ips_online(ha, scb)) {
3888 ips_inquiry(ha, scb);
3895 ips_reqsen(ha, scb);
3907 if (!ips_online(ha, scb)
3908 || !ips_msense(ha, scb)) {
3914 if (ips_online(ha, scb))
3915 ips_rdcap(ha, scb);
3954 ips_name, ha->host_num,
3959 ips_map_status(ha, scb, sp);
3973 ips_online(ips_ha_t * ha, ips_scb_t * scb)
3981 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
3985 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
3987 && ha->logical_drive_info->drive_info[scb->target_id].state !=
3989 && ha->logical_drive_info->drive_info[scb->target_id].state !=
3991 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4008 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4043 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4054 (ha->logical_drive_info->
4073 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4082 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4083 (ha->enq->ucMiscFlag & 0x8) == 0) {
4092 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4164 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4193 ips_free(ips_ha_t * ha)
4198 if (ha) {
4199 if (ha->enq) {
4200 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ),
4201 ha->enq, ha->enq_busaddr);
4202 ha->enq = NULL;
4205 kfree(ha->conf);
4206 ha->conf = NULL;
4208 if (ha->adapt) {
4209 dma_free_coherent(&ha->pcidev->dev,
4211 sizeof (IPS_IO_CMD), ha->adapt,
4212 ha->adapt->hw_status_start);
4213 ha->adapt = NULL;
4216 if (ha->logical_drive_info) {
4217 dma_free_coherent(&ha->pcidev->dev,
4219 ha->logical_drive_info,
4220 ha->logical_drive_info_dma_addr);
4221 ha->logical_drive_info = NULL;
4224 kfree(ha->nvram);
4225 ha->nvram = NULL;
4227 kfree(ha->subsys);
4228 ha->subsys = NULL;
4230 if (ha->ioctl_data) {
4231 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
4232 ha->ioctl_data, ha->ioctl_busaddr);
4233 ha->ioctl_data = NULL;
4234 ha->ioctl_datasize = 0;
4235 ha->ioctl_len = 0;
4237 ips_deallocatescbs(ha, ha->max_cmds);
4240 if (ha->mem_ptr) {
4241 iounmap(ha->ioremap_ptr);
4242 ha->ioremap_ptr = NULL;
4243 ha->mem_ptr = NULL;
4246 ha->mem_addr = 0;
4261 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4263 if (ha->scbs) {
4264 dma_free_coherent(&ha->pcidev->dev,
4265 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4266 ha->scbs->sg_list.list,
4267 ha->scbs->sg_busaddr);
4268 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds,
4269 ha->scbs, ha->scbs->scb_busaddr);
4270 ha->scbs = NULL;
4285 ips_allocatescbs(ips_ha_t * ha)
4295 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev,
4296 ha->max_cmds * sizeof (ips_scb_t),
4298 if (ha->scbs == NULL)
4300 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev,
4301 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds,
4304 dma_free_coherent(&ha->pcidev->dev,
4305 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4310 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4312 for (i = 0; i < ha->max_cmds; i++) {
4313 scb_p = &ha->scbs[i];
4316 if (IPS_USE_ENH_SGLIST(ha)) {
4320 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4325 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4329 if (i < ha->max_cmds - 1) {
4330 scb_p->q_next = ha->scb_freelist;
4331 ha->scb_freelist = scb_p;
4349 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4363 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4366 ha->dummy->op_code = 0xFF;
4367 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4369 ha->dummy->command_id = IPS_MAX_CMDS;
4378 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4394 ips_getscb(ips_ha_t * ha)
4400 if ((scb = ha->scb_freelist) == NULL) {
4405 ha->scb_freelist = scb->q_next;
4409 ips_init_scb(ha, scb);
4426 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4433 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr,
4437 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4438 scb->q_next = ha->scb_freelist;
4439 ha->scb_freelist = scb;
4453 ips_isinit_copperhead(ips_ha_t * ha)
4460 isr = inb(ha->io_addr + IPS_REG_HISR);
4461 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4479 ips_isinit_copperhead_memio(ips_ha_t * ha)
4486 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4487 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4505 ips_isinit_morpheus(ips_ha_t * ha)
4512 if (ips_isintr_morpheus(ha))
4513 ips_flush_and_reset(ha);
4515 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4516 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4537 ips_flush_and_reset(ips_ha_t *ha)
4546 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t),
4550 ips_init_scb(ha, scb);
4564 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4571 done = ips_poll_for_flush_complete(ha);
4580 (*ha->func.reset) (ha);
4582 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma);
4597 ips_poll_for_flush_complete(ips_ha_t * ha)
4602 cstatus.value = (*ha->func.statupd) (ha);
4624 ips_enable_int_copperhead(ips_ha_t * ha)
4628 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4629 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4641 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4645 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4646 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4658 ips_enable_int_morpheus(ips_ha_t * ha)
4664 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4666 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4667 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4680 ips_init_copperhead(ips_ha_t * ha)
4691 Isr = inb(ha->io_addr + IPS_REG_HISR);
4703 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4704 outb(Isr, ha->io_addr + IPS_REG_HISR);
4708 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4717 Isr = inb(ha->io_addr + IPS_REG_HISR);
4729 inb(ha->io_addr + IPS_REG_ISPR);
4730 outb(Isr, ha->io_addr + IPS_REG_HISR);
4734 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4748 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4751 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4753 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4755 outl(0, ha->io_addr + IPS_REG_NDAE);
4758 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4773 ips_init_copperhead_memio(ips_ha_t * ha)
4784 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4796 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4797 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4801 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4810 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4822 readb(ha->mem_ptr + IPS_REG_ISPR);
4823 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4827 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4841 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4844 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4846 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4848 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4851 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4867 ips_init_morpheus(ips_ha_t * ha)
4879 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4890 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4896 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4899 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4904 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4907 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4915 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4924 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4927 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4935 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4946 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4952 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4956 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4959 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4961 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4968 ha->requires_esl = 1;
4984 ips_reset_copperhead(ips_ha_t * ha)
4991 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
4998 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5003 outb(0, ha->io_addr + IPS_REG_SCPR);
5008 if ((*ha->func.init) (ha))
5029 ips_reset_copperhead_memio(ips_ha_t * ha)
5036 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5043 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5048 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5053 if ((*ha->func.init) (ha))
5074 ips_reset_morpheus(ips_ha_t * ha)
5082 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5089 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5095 pci_read_config_byte(ha->pcidev, 4, &junk);
5097 if ((*ha->func.init) (ha))
5118 ips_statinit(ips_ha_t * ha)
5124 ha->adapt->p_status_start = ha->adapt->status;
5125 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5126 ha->adapt->p_status_tail = ha->adapt->status;
5128 phys_status_start = ha->adapt->hw_status_start;
5129 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5131 ha->io_addr + IPS_REG_SQER);
5133 ha->io_addr + IPS_REG_SQHR);
5134 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5136 ha->adapt->hw_status_tail = phys_status_start;
5149 ips_statinit_memio(ips_ha_t * ha)
5155 ha->adapt->p_status_start = ha->adapt->status;
5156 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5157 ha->adapt->p_status_tail = ha->adapt->status;
5159 phys_status_start = ha->adapt->hw_status_start;
5160 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5162 ha->mem_ptr + IPS_REG_SQER);
5163 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5164 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5166 ha->adapt->hw_status_tail = phys_status_start;
5179 ips_statupd_copperhead(ips_ha_t * ha)
5183 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5184 ha->adapt->p_status_tail++;
5185 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5187 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5188 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5191 outl(ha->adapt->hw_status_tail,
5192 ha->io_addr + IPS_REG_SQTR);
5194 return (ha->adapt->p_status_tail->value);
5207 ips_statupd_copperhead_memio(ips_ha_t * ha)
5211 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5212 ha->adapt->p_status_tail++;
5213 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5215 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5216 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5219 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5221 return (ha->adapt->p_status_tail->value);
5234 ips_statupd_morpheus(ips_ha_t * ha)
5240 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5255 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5265 ha->host_num,
5271 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5277 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5284 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5286 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5293 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5294 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5309 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5319 ha->host_num,
5325 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5330 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5337 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5339 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5346 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5347 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5362 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5370 ha->host_num,
5376 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5379 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5394 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5402 ha->host_num,
5408 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5411 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5426 ips_isintr_copperhead(ips_ha_t * ha)
5432 Isr = inb(ha->io_addr + IPS_REG_HISR);
5443 outb(Isr, ha->io_addr + IPS_REG_HISR);
5459 ips_isintr_copperhead_memio(ips_ha_t * ha)
5465 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5476 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5492 ips_isintr_morpheus(ips_ha_t * ha)
5498 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5516 ips_wait(ips_ha_t * ha, int time, int intr)
5530 if (!ha->waitflag) {
5536 if (!ha->waitflag) {
5553 (*ha->func.intr) (ha);
5574 ips_write_driver_status(ips_ha_t * ha, int intr)
5578 if (!ips_readwrite_page5(ha, false, intr)) {
5579 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5587 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5590 ips_name, ha->host_num, ha->nvram->signature);
5591 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5596 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5597 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5598 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5599 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5600 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5601 ha->nvram->bios_low[3]);
5603 ips_get_bios_version(ha, intr);
5606 ha->nvram->operating_system = IPS_OS_LINUX;
5607 ha->nvram->adapter_type = ha->ad_type;
5608 memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5609 memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5610 memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5611 memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5613 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5616 if (!ips_readwrite_page5(ha, true, intr)) {
5617 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5624 ha->slot_num = ha->nvram->adapter_slot;
5639 ips_read_adapter_status(ips_ha_t * ha, int intr)
5646 scb = &ha->scbs[ha->max_cmds - 1];
5648 ips_init_scb(ha, scb);
5654 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5659 scb->data_len = sizeof (*ha->enq);
5660 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5664 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5682 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5689 scb = &ha->scbs[ha->max_cmds - 1];
5691 ips_init_scb(ha, scb);
5697 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5702 scb->data_len = sizeof (*ha->subsys);
5703 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5707 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5712 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5726 ips_read_config(ips_ha_t * ha, int intr)
5736 ha->conf->init_id[i] = 7;
5738 scb = &ha->scbs[ha->max_cmds - 1];
5740 ips_init_scb(ha, scb);
5746 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5747 scb->data_len = sizeof (*ha->conf);
5748 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5752 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5756 memset(ha->conf, 0, sizeof (IPS_CONF));
5760 ha->conf->init_id[i] = 7;
5770 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5784 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5791 scb = &ha->scbs[ha->max_cmds - 1];
5793 ips_init_scb(ha, scb);
5799 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5804 scb->data_len = sizeof (*ha->nvram);
5805 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5807 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5811 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5815 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5820 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5834 ips_clear_adapter(ips_ha_t * ha, int intr)
5841 scb = &ha->scbs[ha->max_cmds - 1];
5843 ips_init_scb(ha, scb);
5849 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5858 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5864 ips_init_scb(ha, scb);
5870 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5879 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5897 ips_ffdc_reset(ips_ha_t * ha, int intr)
5903 scb = &ha->scbs[ha->max_cmds - 1];
5905 ips_init_scb(ha, scb);
5910 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5911 scb->cmd.ffdc.reset_count = ha->reset_count;
5915 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5918 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5931 ips_ffdc_time(ips_ha_t * ha)
5937 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5939 scb = &ha->scbs[ha->max_cmds - 1];
5941 ips_init_scb(ha, scb);
5946 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5951 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5954 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5966 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time)
5996 ips_erase_bios(ips_ha_t * ha)
6006 outl(0, ha->io_addr + IPS_REG_FLAP);
6007 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6010 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6011 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6015 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6016 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6020 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6021 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6025 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6026 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6032 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6033 outl(0, ha->io_addr + IPS_REG_FLAP);
6037 status = inb(ha->io_addr + IPS_REG_FLDP);
6051 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6052 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6058 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6059 outl(0, ha->io_addr + IPS_REG_FLAP);
6063 status = inb(ha->io_addr + IPS_REG_FLDP);
6087 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6088 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6092 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6093 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6108 ips_erase_bios_memio(ips_ha_t * ha)
6118 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6119 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6122 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6123 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6127 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6128 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6132 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6133 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6137 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6138 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6144 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6145 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6149 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6163 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6164 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6170 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6171 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6175 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6199 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6200 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6204 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6205 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6220 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6233 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6234 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6237 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6238 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6241 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6242 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6248 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6249 outl(0, ha->io_addr + IPS_REG_FLAP);
6253 status = inb(ha->io_addr + IPS_REG_FLDP);
6264 outl(0, ha->io_addr + IPS_REG_FLAP);
6265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6268 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6269 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6278 outl(0, ha->io_addr + IPS_REG_FLAP);
6279 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6282 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6283 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6291 outl(0, ha->io_addr + IPS_REG_FLAP);
6292 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6295 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6296 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6311 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6324 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6325 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6328 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6329 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6332 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6333 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6339 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6340 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6344 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6355 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6356 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6359 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6360 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6369 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6370 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6373 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6382 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6383 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6386 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6387 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6402 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6411 outl(0, ha->io_addr + IPS_REG_FLAP);
6412 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6415 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6418 outl(1, ha->io_addr + IPS_REG_FLAP);
6419 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6421 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6427 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6428 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6431 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6451 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6460 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6461 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6464 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6467 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6468 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6470 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6476 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6477 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6481 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6500 ips_abort_init(ips_ha_t * ha, int index)
6502 ha->active = 0;
6503 ips_free(ha);
6639 ips_ha_t *ha, *oldha = ips_ha[index];
6646 ha = IPS_HA(sh);
6647 memcpy(ha, oldha, sizeof (ips_ha_t));
6649 /* Install the interrupt handler with the new ha */
6650 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6651 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6659 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6665 sh->max_id = ha->ntargets;
6666 sh->max_lun = ha->nlun;
6667 sh->max_channel = ha->nbus - 1;
6668 sh->can_queue = ha->max_cmds - 1;
6670 if (scsi_add_host(sh, &ha->pcidev->dev))
6674 ips_ha[index] = ha;
6681 free_irq(ha->pcidev->irq, ha);
6816 ips_ha_t *ha;
6876 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6877 if (ha == NULL) {
6879 "Unable to allocate temporary ha struct\n");
6884 ips_ha[index] = ha;
6885 ha->active = 1;
6888 ha->io_addr = io_addr;
6889 ha->io_len = io_len;
6890 ha->mem_addr = mem_addr;
6891 ha->mem_len = mem_len;
6892 ha->mem_ptr = mem_ptr;
6893 ha->ioremap_ptr = ioremap_ptr;
6894 ha->host_num = (uint32_t) index;
6895 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6896 ha->pcidev = pci_dev;
6904 if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) &&
6905 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) {
6906 (ha)->flags |= IPS_HA_ENH_SG;
6908 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) {
6910 return ips_abort_init(ha, index);
6918 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ),
6919 &ha->enq_busaddr, GFP_KERNEL);
6920 if (!ha->enq) {
6923 return ips_abort_init(ha, index);
6926 ha->adapt = dma_alloc_coherent(&pci_dev->dev,
6929 if (!ha->adapt) {
6932 return ips_abort_init(ha, index);
6934 ha->adapt->hw_status_start = dma_address;
6935 ha->dummy = (void *) (ha->adapt + 1);
6939 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev,
6941 if (!ha->logical_drive_info) {
6944 return ips_abort_init(ha, index);
6946 ha->logical_drive_info_dma_addr = dma_address;
6949 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
6951 if (!ha->conf) {
6954 return ips_abort_init(ha, index);
6957 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
6959 if (!ha->nvram) {
6962 return ips_abort_init(ha, index);
6965 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
6967 if (!ha->subsys) {
6970 return ips_abort_init(ha, index);
6978 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize,
6979 &ha->ioctl_busaddr, GFP_KERNEL);
6980 ha->ioctl_len = ips_ioctlsize;
6981 if (!ha->ioctl_data) {
6984 return ips_abort_init(ha, index);
6990 ips_setup_funclist(ha);
6992 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
6994 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
6996 ips_reset_morpheus(ha);
7004 if (!(*ha->func.isinit) (ha)) {
7005 if (!(*ha->func.init) (ha)) {
7011 return ips_abort_init(ha, index);
7031 ips_ha_t *ha;
7033 ha = ips_ha[index];
7036 if (!ha->active) {
7042 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7043 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7045 return ips_abort_init(ha, index);
7051 ha->max_cmds = 1;
7052 if (!ips_allocatescbs(ha)) {
7053 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7055 free_irq(ha->pcidev->irq, ha);
7056 return ips_abort_init(ha, index);
7059 if (!ips_hainit(ha)) {
7060 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7062 free_irq(ha->pcidev->irq, ha);
7063 return ips_abort_init(ha, index);
7066 ips_deallocatescbs(ha, 1);
7069 if (!ips_allocatescbs(ha)) {
7070 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7072 free_irq(ha->pcidev->irq, ha);
7073 return ips_abort_init(ha, index);