drivers/pwm/pwm-microchip-core.c

107 	 * before attempting to read its state. Reading the registers yields
133 static u64 mchp_core_pwm_calc_duty(const struct pwm_state *state, u64 clk_rate,
145 	duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp);
151 				     const struct pwm_state *state, u64 duty_steps,
167 	if (state->polarity == PWM_POLARITY_INVERSED) {
184 static int mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate,
211 	tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
274 				      const struct pwm_state *state)
283 	if (!state->enabled) {
284 		mchp_core_pwm_enable(chip, pwm, false, pwm->state.period);
297 	ret = mchp_core_pwm_calc_period(state, clk_rate, &prescale, &period_steps);
337 	duty_steps = mchp_core_pwm_calc_duty(state, clk_rate, prescale, period_steps);
352 	mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
354 	mchp_core_pwm_enable(chip, pwm, true, pwm->state.period);
360 			       const struct pwm_state *state)
369 	ret = mchp_core_pwm_apply_locked(chip, pwm, state);
377 				   struct pwm_state *state)
389 		state->enabled = true;
391 		state->enabled = false;
411 	state->period = (period_steps + 1) * (prescale + 1);
412 	state->period *= NSEC_PER_SEC;
413 	state->period = DIV64_U64_ROUND_UP(state->period, rate);
421 		state->duty_cycle = state->period;
422 		state->period *= 2;
425 		state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC;
426 		state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate);
429 	state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;