Lines Matching refs:pctl
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
284 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
298 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
370 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
379 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
430 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
433 if (pctl->hwlock) {
434 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
437 dev_err(pctl->dev, "Can't get hwspinlock\n");
442 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
444 if (pctl->hwlock)
445 hwspin_unlock_in_atomic(pctl->hwlock);
457 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
466 spin_lock_irqsave(&pctl->irqmux_lock, flags);
468 if (pctl->irqmux_map & BIT(hwirq)) {
469 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
472 pctl->irqmux_map |= BIT(hwirq);
475 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
494 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
500 spin_lock_irqsave(&pctl->irqmux_lock, flags);
501 pctl->irqmux_map &= ~BIT(hwirq);
502 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
514 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
518 for (i = 0; i < pctl->ngroups; i++) {
519 struct stm32_pinctrl_group *grp = pctl->groups + i;
528 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
533 for (i = 0; i < pctl->npins; i++) {
534 const struct stm32_desc_pin *pin = pctl->pins + i;
549 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
554 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
565 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
580 struct stm32_pinctrl *pctl;
590 pctl = pinctrl_dev_get_drvdata(pctldev);
594 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
636 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
641 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
643 dev_err(pctl->dev, "unable to match pin %d to group\n",
649 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
696 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
698 return pctl->ngroups;
704 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
706 return pctl->groups[group].name;
714 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
716 *pins = (unsigned *)&pctl->groups[group].pin;
749 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
751 *groups = pctl->grp_names;
752 *num_groups = pctl->ngroups;
760 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
769 if (pctl->hwlock) {
770 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
773 dev_err(pctl->dev, "Can't get hwspinlock\n");
788 if (pctl->hwlock)
789 hwspin_unlock_in_atomic(pctl->hwlock);
825 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
826 struct stm32_pinctrl_group *g = pctl->groups + group;
832 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
838 dev_err(pctl->dev, "No gpio range defined.\n");
863 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
868 dev_err(pctl->dev, "No gpio range defined.\n");
873 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
895 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
902 if (pctl->hwlock) {
903 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
906 dev_err(pctl->dev, "Can't get hwspinlock\n");
916 if (pctl->hwlock)
917 hwspin_unlock_in_atomic(pctl->hwlock);
946 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
953 if (pctl->hwlock) {
954 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
957 dev_err(pctl->dev, "Can't get hwspinlock\n");
967 if (pctl->hwlock)
968 hwspin_unlock_in_atomic(pctl->hwlock);
997 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1004 if (pctl->hwlock) {
1005 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1008 dev_err(pctl->dev, "Can't get hwspinlock\n");
1018 if (pctl->hwlock)
1019 hwspin_unlock_in_atomic(pctl->hwlock);
1069 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1076 dev_err(pctl->dev, "No gpio range defined.\n");
1084 dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1122 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1124 *config = pctl->groups[group].config;
1132 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1133 struct stm32_pinctrl_group *g = &pctl->groups[group];
1168 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1171 struct stm32_desc_pin *pins = pctl->pins;
1174 for (i = 0; i < pctl->npins; i++) {
1186 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1242 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1266 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
1275 if (stm32_pin_nb < pctl->npins) {
1276 pin_desc = pctl->pins + stm32_pin_nb;
1282 for (i = 0; i < pctl->npins; i++) {
1283 pin_desc = pctl->pins + i;
1290 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1292 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1296 struct device *dev = pctl->dev;
1332 bank_nr = pctl->nbanks;
1340 pinctrl_add_gpio_range(pctl->pctl_dev,
1341 &pctl->banks[bank_nr].range);
1354 bank->secure_control = pctl->match_data->secure_control;
1357 if (pctl->domain) {
1361 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1378 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1424 struct stm32_pinctrl *pctl)
1432 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1433 if (IS_ERR(pctl->regmap))
1434 return PTR_ERR(pctl->regmap);
1436 rm = pctl->regmap;
1458 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1459 if (IS_ERR(pctl->irqmux[i]))
1460 return PTR_ERR(pctl->irqmux[i]);
1468 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1471 pctl->ngroups = pctl->npins;
1474 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1475 sizeof(*pctl->groups), GFP_KERNEL);
1476 if (!pctl->groups)
1480 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1481 sizeof(*pctl->grp_names), GFP_KERNEL);
1482 if (!pctl->grp_names)
1485 for (i = 0; i < pctl->npins; i++) {
1486 const struct stm32_desc_pin *pin = pctl->pins + i;
1487 struct stm32_pinctrl_group *group = pctl->groups + i;
1491 pctl->grp_names[i] = pin->pin.name;
1497 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1503 for (i = 0; i < pctl->match_data->npins; i++) {
1504 p = pctl->match_data->pins + i;
1505 if (pctl->pkg && !(pctl->pkg & p->pkg))
1514 pctl->npins = nb_pins_available;
1524 struct stm32_pinctrl *pctl;
1533 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1534 if (!pctl)
1537 platform_set_drvdata(pdev, pctl);
1540 pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1541 if (IS_ERR(pctl->domain))
1542 return PTR_ERR(pctl->domain);
1543 if (!pctl->domain)
1552 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1555 spin_lock_init(&pctl->irqmux_lock);
1557 pctl->dev = dev;
1558 pctl->match_data = match_data;
1561 if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1562 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1564 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1565 sizeof(*pctl->pins), GFP_KERNEL);
1566 if (!pctl->pins)
1569 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1579 if (pctl->domain) {
1580 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1585 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1590 for (i = 0; i < pctl->npins; i++)
1591 pins[i] = pctl->pins[i].pin;
1593 pctl->pctl_desc.name = dev_name(&pdev->dev);
1594 pctl->pctl_desc.owner = THIS_MODULE;
1595 pctl->pctl_desc.pins = pins;
1596 pctl->pctl_desc.npins = pctl->npins;
1597 pctl->pctl_desc.link_consumers = true;
1598 pctl->pctl_desc.confops = &stm32_pconf_ops;
1599 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1600 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1601 pctl->dev = &pdev->dev;
1603 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1604 pctl);
1606 if (IS_ERR(pctl->pctl_dev)) {
1608 return PTR_ERR(pctl->pctl_dev);
1616 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1618 if (!pctl->banks)
1623 struct stm32_gpio_bank *bank = &pctl->banks[i];
1642 ret = stm32_gpiolib_register_bank(pctl, child);
1646 for (i = 0; i < pctl->nbanks; i++)
1647 clk_disable_unprepare(pctl->banks[i].clk);
1652 pctl->nbanks++;
1661 struct stm32_pinctrl *pctl, u32 pin)
1663 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1670 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1718 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1725 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1728 for (i = 0; i < pctl->nbanks; i++)
1729 clk_disable(pctl->banks[i].clk);
1736 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1737 struct stm32_pinctrl_group *g = pctl->groups;
1740 for (i = 0; i < pctl->nbanks; i++)
1741 clk_enable(pctl->banks[i].clk);
1743 for (i = 0; i < pctl->ngroups; i++, g++)
1744 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);