pinctrl/stm32/pinctrl-stm32.c

157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
160 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
161 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
167 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
169 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
170 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
176 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
177 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
183 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
184 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
190 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
191 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
199 	stm32_gpio_backup_value(bank, offset, value);
204 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
209 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
212 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
225 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
227 	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
232 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
234 	__stm32_gpio_set(bank, offset, value);
240 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
242 	__stm32_gpio_set(bank, offset, value);
250 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
253 	fwspec.fwnode = bank->fwnode;
263 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
268 	stm32_pmx_get_mode(bank, pin, &mode, &alt);
283 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
284 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
291 	if (bank->secure_control) {
293 		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
298 				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
321 	struct stm32_gpio_bank *bank = d->domain->host_data;
325 	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
329 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
330 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
331 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
343 	struct stm32_gpio_bank *bank = d->domain->host_data;
362 	bank->irq_type[d->hwirq] = type;
369 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
370 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
373 	ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
377 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
389 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
391 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
429 	struct stm32_gpio_bank *bank = d->host_data;
430 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
442 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
454 	struct stm32_gpio_bank *bank = d->host_data;
457 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
485 				      bank);
493 	struct stm32_gpio_bank *bank = d->host_data;
494 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
757 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
760 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
767 	spin_lock_irqsave(&bank->lock, flags);
778 	val = readl_relaxed(bank->base + alt_offset);
781 	writel_relaxed(val, bank->base + alt_offset);
783 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
786 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
791 	stm32_gpio_backup_mode(bank, pin, mode, alt);
794 	spin_unlock_irqrestore(&bank->lock, flags);
799 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
807 	spin_lock_irqsave(&bank->lock, flags);
809 	val = readl_relaxed(bank->base + alt_offset);
813 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
817 	spin_unlock_irqrestore(&bank->lock, flags);
828 	struct stm32_gpio_bank *bank;
842 	bank = gpiochip_get_data(range->gc);
848 	return stm32_pmx_set_mode(bank, pin, mode, alt);
855 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
858 	return stm32_pmx_set_mode(bank, pin, !input, 0);
892 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
895 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
900 	spin_lock_irqsave(&bank->lock, flags);
911 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
914 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
919 	stm32_gpio_backup_driving(bank, offset, drive);
922 	spin_unlock_irqrestore(&bank->lock, flags);
927 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
933 	spin_lock_irqsave(&bank->lock, flags);
935 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
938 	spin_unlock_irqrestore(&bank->lock, flags);
943 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
946 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
951 	spin_lock_irqsave(&bank->lock, flags);
962 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
965 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
970 	stm32_gpio_backup_speed(bank, offset, speed);
973 	spin_unlock_irqrestore(&bank->lock, flags);
978 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
984 	spin_lock_irqsave(&bank->lock, flags);
986 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
989 	spin_unlock_irqrestore(&bank->lock, flags);
994 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
997 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1002 	spin_lock_irqsave(&bank->lock, flags);
1013 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1016 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1021 	stm32_gpio_backup_bias(bank, offset, bias);
1024 	spin_unlock_irqrestore(&bank->lock, flags);
1029 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1035 	spin_lock_irqsave(&bank->lock, flags);
1037 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1040 	spin_unlock_irqrestore(&bank->lock, flags);
1045 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1051 	spin_lock_irqsave(&bank->lock, flags);
1054 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1057 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1060 	spin_unlock_irqrestore(&bank->lock, flags);
1071 	struct stm32_gpio_bank *bank;
1080 	bank = gpiochip_get_data(range->gc);
1090 		ret = stm32_pconf_set_driving(bank, offset, 0);
1093 		ret = stm32_pconf_set_driving(bank, offset, 1);
1096 		ret = stm32_pconf_set_speed(bank, offset, arg);
1099 		ret = stm32_pconf_set_bias(bank, offset, 0);
1102 		ret = stm32_pconf_set_bias(bank, offset, 1);
1105 		ret = stm32_pconf_set_bias(bank, offset, 2);
1108 		__stm32_gpio_set(bank, offset, arg);
1189 	struct stm32_gpio_bank *bank;
1204 	bank = gpiochip_get_data(range->gc);
1212 	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1213 	bias = stm32_pconf_get_bias(bank, offset);
1220 		val = stm32_pconf_get(bank, offset, true);
1228 		drive = stm32_pconf_get_driving(bank, offset);
1229 		speed = stm32_pconf_get_speed(bank, offset);
1230 		val = stm32_pconf_get(bank, offset, false);
1240 		drive = stm32_pconf_get_driving(bank, offset);
1241 		speed = stm32_pconf_get_speed(bank, offset);
1267 								 struct stm32_gpio_bank *bank,
1270 	unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
1274 	/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
1292 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1294 	struct pinctrl_gpio_range *range = &bank->range;
1303 	if (!IS_ERR(bank->rstc))
1304 		reset_control_deassert(bank->rstc);
1309 	bank->base = devm_ioremap_resource(dev, &res);
1310 	if (IS_ERR(bank->base))
1311 		return PTR_ERR(bank->base);
1313 	err = clk_prepare_enable(bank->clk);
1319 	bank->gpio_chip = stm32_gpio_template;
1321 	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1325 		bank->gpio_chip.base = args.args[1];
1333 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1334 		range->name = bank->gpio_chip.label;
1339 		range->gc = &bank->gpio_chip;
1344 	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1347 	bank->gpio_chip.base = -1;
1349 	bank->gpio_chip.ngpio = npins;
1350 	bank->gpio_chip.fwnode = fwnode;
1351 	bank->gpio_chip.parent = dev;
1352 	bank->bank_nr = bank_nr;
1353 	bank->bank_ioport_nr = bank_ioport_nr;
1354 	bank->secure_control = pctl->match_data->secure_control;
1355 	spin_lock_init(&bank->lock);
1359 		bank->fwnode = fwnode;
1361 		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1362 							   bank->fwnode, &stm32_gpio_domain_ops,
1363 							   bank);
1365 		if (!bank->domain) {
1378 		stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1385 	bank->gpio_chip.names = (const char * const *)names;
1387 	err = gpiochip_add_data(&bank->gpio_chip, bank);
1393 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1397 	clk_disable_unprepare(bank->clk);
1613 		dev_err(dev, "at least one GPIO bank is required\n");
1623 		struct stm32_gpio_bank *bank = &pctl->banks[i];
1626 		bank->rstc = of_reset_control_get_exclusive(np, NULL);
1627 		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1632 		bank->clk = of_clk_get_by_name(np, NULL);
1633 		if (IS_ERR(bank->clk)) {
1635 			return dev_err_probe(dev, PTR_ERR(bank->clk),
1666 	struct stm32_gpio_bank *bank;
1682 	bank = gpiochip_get_data(range->gc);
1684 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1686 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1689 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1694 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1696 		__stm32_gpio_set(bank, offset, val);
1699 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1701 	ret = stm32_pconf_set_driving(bank, offset, val);
1705 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1707 	ret = stm32_pconf_set_speed(bank, offset, val);
1711 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1713 	ret = stm32_pconf_set_bias(bank, offset, val);
1718 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);