drivers/pinctrl/pinctrl-ingenic.c

3262 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
3266 	regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3271 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
3274 	if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3275 		regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3285 	regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3288 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3296 	regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3297 			jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
3300 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3302 	regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3303 			jzgc->jzpc->info->reg_offset),
3304 			jzgc->gc.base / PINS_PER_GPIO_CHIP);
3307 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3318 	regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3321 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3324 	unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
3329 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3332 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3333 		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
3334 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3335 		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
3337 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
3340 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3369 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
3372 	} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3376 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3377 		jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3382 	if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3383 		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3384 		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3385 		ingenic_gpio_shadow_set_bit_load(jzgc);
3386 		ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
3387 	} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
3388 		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3389 		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3390 		ingenic_gpio_shadow_set_bit_load(jzgc);
3392 		ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3393 		ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3400 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3403 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3404 		ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3406 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
3412 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3415 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3416 		ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3418 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
3424 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3429 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3430 		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
3431 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3432 		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
3434 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
3442 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3447 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3448 		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
3449 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3450 		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
3452 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
3460 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3465 	    !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3470 		high = ingenic_gpio_get_value(jzgc, irq);
3472 			irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
3474 			irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
3477 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3478 		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
3479 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3480 		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
3482 		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
3488 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3505 	if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3511 		bool high = ingenic_gpio_get_value(jzgc, irq);
3516 	irq_set_type(jzgc, irq, type);
3523 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3525 	return irq_set_irq_wake(jzgc->irq, on);
3531 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3537 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3538 		flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
3539 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3540 		flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
3542 		flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3552 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3554 	ingenic_gpio_set_value(jzgc, offset, value);
3559 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3561 	return (int) ingenic_gpio_get_value(jzgc, offset);
3640 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3641 	struct ingenic_pinctrl *jzpc = jzgc->jzpc;
4157 	struct ingenic_gpio_chip *jzgc;
4169 	jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4170 	if (!jzgc)
4173 	jzpc->gc = &jzgc->gc;
4175 	jzgc->jzpc = jzpc;
4176 	jzgc->reg_base = bank * jzpc->info->reg_offset;
4178 	jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4179 	if (!jzgc->gc.label)
4186 	jzgc->gc.base = bank * 32;
4188 	jzgc->gc.ngpio = 32;
4189 	jzgc->gc.parent = dev;
4190 	jzgc->gc.fwnode = fwnode;
4191 	jzgc->gc.owner = THIS_MODULE;
4193 	jzgc->gc.set = ingenic_gpio_set;
4194 	jzgc->gc.get = ingenic_gpio_get;
4195 	jzgc->gc.direction_input = pinctrl_gpio_direction_input;
4196 	jzgc->gc.direction_output = ingenic_gpio_direction_output;
4197 	jzgc->gc.get_direction = ingenic_gpio_get_direction;
4198 	jzgc->gc.request = gpiochip_generic_request;
4199 	jzgc->gc.free = gpiochip_generic_free;
4206 	jzgc->irq = err;
4208 	girq = &jzgc->gc.irq;
4217 	girq->parents[0] = jzgc->irq;
4221 	err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);