pinctrl/nuvoton/pinctrl-npcm8xx.c

140 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
143 		   ioread32(bank->base + NPCM8XX_GP_N_DIN),
144 		   ioread32(bank->base + NPCM8XX_GP_N_DOUT),
145 		   ioread32(bank->base + NPCM8XX_GP_N_IEM),
146 		   ioread32(bank->base + NPCM8XX_GP_N_OE));
148 		   ioread32(bank->base + NPCM8XX_GP_N_PU),
149 		   ioread32(bank->base + NPCM8XX_GP_N_PD),
150 		   ioread32(bank->base + NPCM8XX_GP_N_DBNC),
151 		   ioread32(bank->base + NPCM8XX_GP_N_POL));
153 		   ioread32(bank->base + NPCM8XX_GP_N_EVTYP),
154 		   ioread32(bank->base + NPCM8XX_GP_N_EVBE),
155 		   ioread32(bank->base + NPCM8XX_GP_N_EVEN),
156 		   ioread32(bank->base + NPCM8XX_GP_N_EVST));
158 		   ioread32(bank->base + NPCM8XX_GP_N_OTYP),
159 		   ioread32(bank->base + NPCM8XX_GP_N_OSRC),
160 		   ioread32(bank->base + NPCM8XX_GP_N_ODSC));
162 		   ioread32(bank->base + NPCM8XX_GP_N_OBL0),
163 		   ioread32(bank->base + NPCM8XX_GP_N_OBL1),
164 		   ioread32(bank->base + NPCM8XX_GP_N_OBL2),
165 		   ioread32(bank->base + NPCM8XX_GP_N_OBL3));
167 		   ioread32(bank->base + NPCM8XX_GP_N_SPLCK),
168 		   ioread32(bank->base + NPCM8XX_GP_N_MPLCK));
173 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
180 	return bank->direction_input(chip, offset);
186 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
193 	return bank->direction_output(chip, offset, value);
198 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
205 	return bank->request(chip, offset);
211 	struct npcm8xx_gpio *bank;
216 	bank = gpiochip_get_data(gc);
220 	sts = ioread32(bank->base + NPCM8XX_GP_N_EVST);
221 	en  = ioread32(bank->base + NPCM8XX_GP_N_EVEN);
230 	struct npcm8xx_gpio *bank =
236 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
237 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
240 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
241 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
244 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
247 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
250 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
257 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
260 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
269 	struct npcm8xx_gpio *bank =
273 	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST);
278 	struct npcm8xx_gpio *bank =
282 	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC);
287 	struct npcm8xx_gpio *bank =
291 	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS);
1859 static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
1862 	int gpio = pin % bank->gc.ngpio;
1867 		return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask;
1877 static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
1881 	void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;
1882 	int gpio = BIT(pin % bank->gc.ngpio);
1887 			npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio);
1890 			npcm_gpio_set(&bank->gc, OSRC_Offset, gpio);
1920 	struct npcm8xx_gpio *bank =
1922 	int gpio = pin % bank->gc.ngpio;
1931 	val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;
1933 	dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
1941 	struct npcm8xx_gpio *bank =
1943 	int gpio = BIT(pin % bank->gc.ngpio);
1949 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
1951 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
2072 	struct npcm8xx_gpio *bank =
2074 	int gpio = BIT(offset % bank->gc.ngpio);
2077 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2079 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2094 static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
2097 	void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4);
2102 		if (bank->debounce.set_val[i]) {
2103 			if (bank->debounce.nanosec_val[i] == nanosecs) {
2105 				npcm_gpio_set(&bank->gc, DBNCS_offset,
2110 			bank->debounce.set_val[i] = true;
2111 			bank->debounce.nanosec_val[i] = nanosecs;
2113 			npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select);
2116 				iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2119 				iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2122 				iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2125 				iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2128 				iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2131 				iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2134 				iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2137 				iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2147 					  bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2163 	struct npcm8xx_gpio *bank =
2165 	int gpio = BIT(pin % bank->gc.ngpio);
2169 		ret = debounce_timing_setting(bank, pin % bank->gc.ngpio,
2174 			npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC,
2179 	npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio);
2190 	struct npcm8xx_gpio *bank =
2192 	int gpio = pin % bank->gc.ngpio;
2201 		pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask;
2202 		pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask;
2212 		ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
2213 		oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
2220 		rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask);
2223 		rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask;
2226 		rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask;
2234 		rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
2252 	struct npcm8xx_gpio *bank =
2255 	int gpio = BIT(pin % bank->gc.ngpio);
2259 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
2260 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
2263 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
2264 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
2267 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
2268 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
2271 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2272 		bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
2275 		bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
2276 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2279 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2282 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2287 		return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
2331 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
2333 	return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent),
2334 				      bank->pinctrl_id, bank->gc.base,
2335 				      bank->gc.ngpio);
2363 			return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id);
2367 			return dev_err_probe(dev, ret, "No IRQ for GPIO bank %u\n", id);