phy/mediatek/phy-mtk-xsphy.c

112 	void __iomem *pbase = inst->port_base;
122 	mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
126 	mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
129 	mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
133 	mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
136 	readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
139 	fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
142 	mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
145 	mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
161 	mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val);
164 	mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
170 	void __iomem *pbase = inst->port_base;
173 	mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN);
175 	mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN);
181 	void __iomem *pbase = inst->port_base;
184 	mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
186 	mtk_phy_update_bits(pbase + XSP_U2PHYDTM1,
196 	void __iomem *pbase = inst->port_base;
199 	mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
201 	mtk_phy_update_bits(pbase + XSP_U2PHYDTM1,
271 	void __iomem *pbase = inst->port_base;
274 		mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
278 		mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
282 		mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
286 		mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
293 	void __iomem *pbase = inst->port_base;
300 		mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04,
304 		mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14,