drivers/pci/quirks.c

922 	u32 val;
925 	pci_read_config_dword(dev, reg, &val);
928 	if (!(val & 1))
930 	base = val & 0xfffc;
966 	u32 val;
969 	pci_read_config_dword(dev, reg, &val);
972 	if (!(val & 1))
976 	base = val & 0xfffc;
977 	mask = (val >> 16) & 0xfc;
1637 	u16 val;
1642 	pci_read_config_word(dev, 0xF2, &val);
1643 	if (val & 0x8) {
1644 		pci_write_config_word(dev, 0xF2, val & (~0x8));
1645 		pci_read_config_word(dev, 0xF2, &val);
1646 		if (val & 0x8)
1648 				 val);
1687 	u32 val;
1693 	val = readl(asus_rcba_base + 0x3418);
1696 	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1723 	u8 val = 0;
1724 	pci_read_config_byte(dev, 0x77, &val);
1725 	if (val & 0x10) {
1727 		pci_write_config_byte(dev, 0x77, val & ~0x10);
1781 	u8 val;
1792 	pci_read_config_byte(dev, 0x50, &val);
1793 	if (val & 0xc0) {
1794 		pci_write_config_byte(dev, 0x50, val & (~0xc0));
1795 		pci_read_config_byte(dev, 0x50, &val);
1796 		if (val & 0xc0)
1798 				 val);
3506 	u8 val;
3508 	rc = pci_read_config_byte(dev, 0x00D0, &val);
3512 	dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3514 	rc = pci_read_config_byte(dev, 0x00D1, &val);
3518 	dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3930 	u32 val;
3949 	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3950 	iowrite32(val, mmio_base + PCH_PP_CONTROL);
3954 		val = ioread32(mmio_base + PCH_PP_STATUS);
3955 		if ((val & 0xb0000000) == 0)
4146 	u32 val;
4156 	val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4157 	if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4163 	val = ioread32be(bar + HINIC_VF_OP);
4164 	val = val | HINIC_VF_FLR_PROC_BIT;
4165 	iowrite32be(val, bar + HINIC_VF_OP);
4179 		val = ioread32be(bar + HINIC_VF_OP);
4180 		if (!(val & HINIC_VF_FLR_PROC_BIT))
4185 	val = ioread32be(bar + HINIC_VF_OP);
4186 	if (!(val & HINIC_VF_FLR_PROC_BIT))
4189 	pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
5704 	u32 val;
5711 	pci_read_config_dword(gpu, 0x488, &val);
5712 	if (val & BIT(25))
5716 	pci_write_config_dword(gpu, 0x488, val | BIT(25));
6087 	u16 val;
6096 	pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
6097 	if (!(val & PCI_ACS_RR))
6104 	pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
6105 	if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
6107 		pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
6198 	u16 dpc, val;
6204 	pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
6205 	if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
6208 	if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) {
6261 	u32 val;
6269 	pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val);
6270 	val |= PCI_ERR_COR_REP_TIMER;
6271 	pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val);