controller/dwc/pcie-qcom.c

27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
225 	int (*get_resources)(struct qcom_pcie *pcie);
226 	int (*init)(struct qcom_pcie *pcie);
227 	int (*post_init)(struct qcom_pcie *pcie);
228 	void (*host_post_init)(struct qcom_pcie *pcie);
229 	void (*deinit)(struct qcom_pcie *pcie);
230 	void (*ltssm_enable)(struct qcom_pcie *pcie);
231 	int (*config_sid)(struct qcom_pcie *pcie);
255 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
257 	gpiod_set_value_cansleep(pcie->reset, 1);
261 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
265 	gpiod_set_value_cansleep(pcie->reset, 0);
271 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
274 	if (pcie->cfg->ops->ltssm_enable)
275 		pcie->cfg->ops->ltssm_enable(pcie);
282 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
286 	if (!pcie->cfg->no_l0s)
314 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
319 	val = readl(pcie->elbi + ELBI_SYS_CTRL);
321 	writel(val, pcie->elbi + ELBI_SYS_CTRL);
324 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
326 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
327 	struct dw_pcie *pci = pcie->pci;
329 	bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064");
372 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
374 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
379 	writel(1, pcie->parf + PARF_PHY_CTRL);
384 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
386 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
387 	struct dw_pcie *pci = pcie->pci;
414 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
416 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
417 	struct dw_pcie *pci = pcie->pci;
424 	val = readl(pcie->parf + PARF_PHY_CTRL);
426 	writel(val, pcie->parf + PARF_PHY_CTRL);
432 	if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
433 	    of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
437 		       pcie->parf + PARF_PCS_DEEMPH);
440 		       pcie->parf + PARF_PCS_SWING);
441 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
444 	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
446 		val = readl(pcie->parf + PARF_PHY_CTRL);
449 		writel(val, pcie->parf + PARF_PHY_CTRL);
453 	val = readl(pcie->parf + PARF_PHY_REFCLK);
455 	if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
458 	writel(val, pcie->parf + PARF_PHY_REFCLK);
469 	qcom_pcie_clear_hpc(pcie->pci);
474 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
476 	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
477 	struct dw_pcie *pci = pcie->pci;
498 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
500 	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
507 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
509 	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
510 	struct dw_pcie *pci = pcie->pci;
542 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
545 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
548 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
551 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
554 	qcom_pcie_clear_hpc(pcie->pci);
559 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
564 	val = readl(pcie->parf + PARF_LTSSM);
566 	writel(val, pcie->parf + PARF_LTSSM);
569 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
571 	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
572 	struct dw_pcie *pci = pcie->pci;
595 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
597 	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
603 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
605 	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
606 	struct dw_pcie *pci = pcie->pci;
626 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
631 	val = readl(pcie->parf + PARF_PHY_CTRL);
633 	writel(val, pcie->parf + PARF_PHY_CTRL);
636 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
639 	val = readl(pcie->parf + PARF_SYS_CTRL);
641 	writel(val, pcie->parf + PARF_SYS_CTRL);
643 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
645 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
647 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
649 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
651 	qcom_pcie_clear_hpc(pcie->pci);
656 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
658 	struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
659 	struct dw_pcie *pci = pcie->pci;
661 	bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
669 	/* qcom,pcie-ipq4019 is defined without "iface" */
698 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
700 	struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
706 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
708 	struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
709 	struct dw_pcie *pci = pcie->pci;
738 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
740 	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
741 	struct dw_pcie *pci = pcie->pci;
770 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
772 	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
777 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
779 	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
780 	struct dw_pcie *pci = pcie->pci;
822 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
824 	struct dw_pcie *pci = pcie->pci;
828 	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
830 	val = readl(pcie->parf + PARF_PHY_CTRL);
832 	writel(val, pcie->parf + PARF_PHY_CTRL);
834 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
839 		pcie->parf + PARF_SYS_CTRL);
840 	writel(0, pcie->parf + PARF_Q2A_FLUSH);
860 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
862 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
863 	struct dw_pcie *pci = pcie->pci;
914 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
916 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
917 	struct dw_pcie *pci = pcie->pci;
950 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
953 	val = readl(pcie->parf + PARF_PHY_CTRL);
955 	writel(val, pcie->parf + PARF_PHY_CTRL);
958 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
961 	val = readl(pcie->parf + PARF_SYS_CTRL);
963 	writel(val, pcie->parf + PARF_SYS_CTRL);
965 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
967 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
970 	val = readl(pcie->parf + PARF_PM_CTRL);
972 	writel(val, pcie->parf + PARF_PM_CTRL);
974 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
976 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
987 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
989 	qcom_pcie_clear_aspm_l0s(pcie->pci);
990 	qcom_pcie_clear_hpc(pcie->pci);
1007 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)
1009 	struct dw_pcie_rp *pp = &pcie->pci->pp;
1014 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1016 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1023 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
1032 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
1033 	struct device *dev = pcie->pci->dev;
1044 	val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1046 	writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1099 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1101 	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1102 	struct dw_pcie *pci = pcie->pci;
1123 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1125 	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1130 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1132 	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1133 	struct device *dev = pcie->pci->dev;
1159 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1161 	struct dw_pcie *pci = pcie->pci;
1167 		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
1169 	val = readl(pcie->parf + PARF_PHY_CTRL);
1171 	writel(val, pcie->parf + PARF_PHY_CTRL);
1173 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
1175 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1177 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1185 		pcie->parf + PARF_SYS_CTRL);
1187 	writel(0, pcie->parf + PARF_Q2A_FLUSH);
1203 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1219 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
1222 	qcom_ep_reset_assert(pcie);
1224 	ret = pcie->cfg->ops->init(pcie);
1228 	ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1232 	ret = phy_power_on(pcie->phy);
1236 	if (pcie->cfg->ops->post_init) {
1237 		ret = pcie->cfg->ops->post_init(pcie);
1242 	qcom_ep_reset_deassert(pcie);
1244 	if (pcie->cfg->ops->config_sid) {
1245 		ret = pcie->cfg->ops->config_sid(pcie);
1253 	qcom_ep_reset_assert(pcie);
1255 	phy_power_off(pcie->phy);
1257 	pcie->cfg->ops->deinit(pcie);
1265 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
1267 	qcom_ep_reset_assert(pcie);
1268 	phy_power_off(pcie->phy);
1269 	pcie->cfg->ops->deinit(pcie);
1275 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
1277 	if (pcie->cfg->ops->host_post_init)
1278 		pcie->cfg->ops->host_post_init(pcie);
1403 static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1405 	struct dw_pcie *pci = pcie->pci;
1408 	pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1409 	if (IS_ERR(pcie->icc_mem))
1410 		return PTR_ERR(pcie->icc_mem);
1417 	 * for the pcie-mem path.
1419 	ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
1429 static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
1431 	struct dw_pcie *pci = pcie->pci;
1436 	if (!pcie->icc_mem)
1449 	ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
1458 	struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);
1461 		   readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
1464 		   readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
1467 		   readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
1470 		   readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
1473 		   readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
1478 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
1480 	struct dw_pcie *pci = pcie->pci;
1488 	pcie->debugfs = debugfs_create_dir(name, NULL);
1489 	debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs,
1497 	struct qcom_pcie *pcie;
1509 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1510 	if (!pcie)
1526 	pcie->pci = pci;
1528 	pcie->cfg = pcie_cfg;
1530 	pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1531 	if (IS_ERR(pcie->reset)) {
1532 		ret = PTR_ERR(pcie->reset);
1536 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1537 	if (IS_ERR(pcie->parf)) {
1538 		ret = PTR_ERR(pcie->parf);
1542 	pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1543 	if (IS_ERR(pcie->elbi)) {
1544 		ret = PTR_ERR(pcie->elbi);
1551 		pcie->mhi = devm_ioremap_resource(dev, res);
1552 		if (IS_ERR(pcie->mhi)) {
1553 			ret = PTR_ERR(pcie->mhi);
1558 	pcie->phy = devm_phy_optional_get(dev, "pciephy");
1559 	if (IS_ERR(pcie->phy)) {
1560 		ret = PTR_ERR(pcie->phy);
1564 	ret = qcom_pcie_icc_init(pcie);
1568 	ret = pcie->cfg->ops->get_resources(pcie);
1574 	ret = phy_init(pcie->phy);
1578 	platform_set_drvdata(pdev, pcie);
1586 	qcom_pcie_icc_update(pcie);
1588 	if (pcie->mhi)
1589 		qcom_pcie_init_debugfs(pcie);
1594 	phy_exit(pcie->phy);
1604 	struct qcom_pcie *pcie = dev_get_drvdata(dev);
1611 	ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
1632 	if (!dw_pcie_link_up(pcie->pci)) {
1633 		qcom_pcie_host_deinit(&pcie->pci->pp);
1634 		pcie->suspended = true;
1642 	struct qcom_pcie *pcie = dev_get_drvdata(dev);
1645 	if (pcie->suspended) {
1646 		ret = qcom_pcie_host_init(&pcie->pci->pp);
1650 		pcie->suspended = false;
1653 	qcom_pcie_icc_update(pcie);
1659 	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1660 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1661 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1662 	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1663 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1664 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1665 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1666 	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1667 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1668 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1669 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
1670 	{ .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
1671 	{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1672 	{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1673 	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
1674 	{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1675 	{ .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1676 	{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1677 	{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1678 	{ .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1679 	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1680 	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1681 	{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1682 	{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
1705 		.name = "qcom-pcie",