Lines Matching defs:rt2x00dev
54 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
59 mutex_lock(&rt2x00dev->csr_mutex);
65 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
72 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
75 mutex_unlock(&rt2x00dev->csr_mutex);
78 static u8 rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
84 mutex_lock(&rt2x00dev->csr_mutex);
94 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
100 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
102 WAIT_FOR_BBP(rt2x00dev, ®);
107 mutex_unlock(&rt2x00dev->csr_mutex);
112 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
117 mutex_lock(&rt2x00dev->csr_mutex);
123 if (WAIT_FOR_RF(rt2x00dev, ®)) {
130 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg);
131 rt2x00_rf_write(rt2x00dev, word, value);
134 mutex_unlock(&rt2x00dev->csr_mutex);
137 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
143 mutex_lock(&rt2x00dev->csr_mutex);
149 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
154 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
156 reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR);
159 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg);
162 mutex_unlock(&rt2x00dev->csr_mutex);
168 struct rt2x00_dev *rt2x00dev = eeprom->data;
171 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
183 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
231 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
235 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13);
247 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ);
249 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
252 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
255 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
256 (led->rt2x00dev->led_mcu_reg & 0xff),
257 ((led->rt2x00dev->led_mcu_reg >> 8)));
259 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
261 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
264 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
265 (led->rt2x00dev->led_mcu_reg & 0xff),
266 ((led->rt2x00dev->led_mcu_reg >> 8)));
273 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
286 reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14);
289 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg);
294 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
298 led->rt2x00dev = rt2x00dev;
309 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
321 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
340 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2);
343 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3);
365 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
369 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
377 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4);
379 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg);
402 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2);
407 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg);
411 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3);
416 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg);
422 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
433 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0);
441 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
443 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
444 !rt2x00dev->intf_ap_count);
451 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
454 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
465 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
467 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
475 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2,
484 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4,
490 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
496 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0);
499 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
502 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4);
506 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5,
514 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
517 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
521 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9);
523 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
525 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8);
529 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg);
533 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
540 r3 = rt61pci_bbp_read(rt2x00dev, 3);
541 r4 = rt61pci_bbp_read(rt2x00dev, 4);
542 r77 = rt61pci_bbp_read(rt2x00dev, 77);
544 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
553 (rt2x00dev->curr_band != NL80211_BAND_5GHZ));
558 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)
567 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)
574 rt61pci_bbp_write(rt2x00dev, 77, r77);
575 rt61pci_bbp_write(rt2x00dev, 3, r3);
576 rt61pci_bbp_write(rt2x00dev, 4, r4);
579 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
586 r3 = rt61pci_bbp_read(rt2x00dev, 3);
587 r4 = rt61pci_bbp_read(rt2x00dev, 4);
588 r77 = rt61pci_bbp_read(rt2x00dev, 77);
590 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
592 !rt2x00_has_cap_frame_type(rt2x00dev));
612 rt61pci_bbp_write(rt2x00dev, 77, r77);
613 rt61pci_bbp_write(rt2x00dev, 3, r3);
614 rt61pci_bbp_write(rt2x00dev, 4, r4);
617 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
622 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13);
630 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
633 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
640 r3 = rt61pci_bbp_read(rt2x00dev, 3);
641 r4 = rt61pci_bbp_read(rt2x00dev, 4);
642 r77 = rt61pci_bbp_read(rt2x00dev, 77);
651 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
663 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
667 rt61pci_bbp_write(rt2x00dev, 77, r77);
668 rt61pci_bbp_write(rt2x00dev, 3, r3);
669 rt61pci_bbp_write(rt2x00dev, 4, r4);
703 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
718 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
720 lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
723 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
727 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
729 reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0);
732 rt2x00dev->curr_band == NL80211_BAND_2GHZ);
734 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
736 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg);
738 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
739 rt61pci_config_antenna_5x(rt2x00dev, ant);
740 else if (rt2x00_rf(rt2x00dev, RF2527))
741 rt61pci_config_antenna_2x(rt2x00dev, ant);
742 else if (rt2x00_rf(rt2x00dev, RF2529)) {
743 if (rt2x00_has_cap_double_antenna(rt2x00dev))
744 rt61pci_config_antenna_2x(rt2x00dev, ant);
746 rt61pci_config_antenna_2529(rt2x00dev, ant);
750 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
757 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
760 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG);
763 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
766 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A);
770 rt2x00dev->lna_gain = lna_gain;
773 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
781 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
783 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
785 r3 = rt61pci_bbp_read(rt2x00dev, 3);
787 rt61pci_bbp_write(rt2x00dev, 3, r3);
794 rt61pci_bbp_write(rt2x00dev, 94, r94);
796 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
797 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
798 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
799 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
803 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
804 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
805 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
806 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
810 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
811 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
812 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
813 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
818 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
823 rf.rf1 = rt2x00_rf_read(rt2x00dev, 1);
824 rf.rf2 = rt2x00_rf_read(rt2x00dev, 2);
825 rf.rf3 = rt2x00_rf_read(rt2x00dev, 3);
826 rf.rf4 = rt2x00_rf_read(rt2x00dev, 4);
828 rt61pci_config_channel(rt2x00dev, &rf, txpower);
831 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
836 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4);
844 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
847 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
856 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11);
858 rt2x00dev->beacon_int - 10);
865 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
868 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
870 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
872 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
873 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
875 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
877 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11);
882 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
884 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
886 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
887 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
889 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
893 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
898 rt61pci_config_lna_gain(rt2x00dev, libconf);
901 rt61pci_config_channel(rt2x00dev, &libconf->rf,
905 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
907 rt61pci_config_retry_limit(rt2x00dev, libconf);
909 rt61pci_config_ps(rt2x00dev, libconf);
915 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
923 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0);
929 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1);
933 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
937 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
943 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
946 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
949 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
958 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
961 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
968 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
978 if (!rt2x00dev->intf_associated)
985 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
993 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1001 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1009 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1022 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1033 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1035 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1043 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1048 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0);
1050 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1053 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
1057 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1066 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1071 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1073 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1076 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1078 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1081 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1083 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1086 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1088 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1097 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1102 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1104 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1107 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1109 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1112 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1114 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1117 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR);
1119 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1122 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0);
1124 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1127 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
1131 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1136 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1146 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1151 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1170 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1199 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1209 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0);
1216 rt2x00_err(rt2x00dev, "Unstable hardware\n");
1225 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1226 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1227 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1228 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1236 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1238 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1242 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1245 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1248 reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR);
1255 rt2x00_err(rt2x00dev, "MCU Control register not ready\n");
1270 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1272 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1);
1275 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1277 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1);
1279 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1327 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1335 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0);
1337 rt2x00dev->tx[0].limit);
1339 rt2x00dev->tx[1].limit);
1341 rt2x00dev->tx[2].limit);
1343 rt2x00dev->tx[3].limit);
1344 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg);
1346 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1);
1348 rt2x00dev->tx[0].desc_size / 4);
1349 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg);
1351 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1352 reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR);
1355 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1357 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1358 reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR);
1361 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1363 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1364 reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR);
1367 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1369 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1370 reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR);
1373 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1375 reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR);
1376 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1378 rt2x00dev->rx->desc_size / 4);
1380 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg);
1382 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1383 reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR);
1386 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg);
1388 reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR);
1393 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1395 reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR);
1400 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1402 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR);
1404 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1409 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1413 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0);
1417 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1419 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1);
1428 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg);
1433 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2);
1442 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg);
1447 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3);
1454 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg);
1456 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7);
1461 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg);
1463 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8);
1468 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg);
1470 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
1477 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1479 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1481 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1483 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9);
1485 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
1487 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1489 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1492 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1498 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1499 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1502 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1503 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1504 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1505 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1507 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1509 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1511 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1519 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1520 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1521 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1522 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1529 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0);
1530 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1);
1531 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2);
1536 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1);
1539 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1541 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1);
1544 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1546 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1);
1548 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1553 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1559 value = rt61pci_bbp_read(rt2x00dev, 0);
1565 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1569 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1576 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1579 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1580 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1581 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1582 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1583 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1584 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1585 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1586 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1587 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1588 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1589 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1590 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1591 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1592 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1593 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1594 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1595 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1596 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1597 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1598 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1599 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1600 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1601 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1602 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1605 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
1610 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1620 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1632 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
1633 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1635 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR);
1636 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1643 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1645 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
1651 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1653 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR);
1663 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1665 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1671 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1672 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1673 tasklet_kill(&rt2x00dev->autowake_tasklet);
1674 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1678 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1685 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1686 rt61pci_init_registers(rt2x00dev) ||
1687 rt61pci_init_bbp(rt2x00dev)))
1693 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR);
1695 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1700 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1705 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1708 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1716 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12);
1719 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1727 reg2 = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12);
1731 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1738 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1745 retval = rt61pci_enable_radio(rt2x00dev);
1748 rt61pci_disable_radio(rt2x00dev);
1752 rt61pci_toggle_irq(rt2x00dev, state);
1758 retval = rt61pci_set_state(rt2x00dev, state);
1766 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1815 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1875 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1885 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
1888 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1898 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1905 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1908 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1913 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base,
1915 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1925 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1928 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1939 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1946 orig_reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9);
1949 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1954 rt2x00mmio_register_write(rt2x00dev,
1960 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1966 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1968 u8 offset = rt2x00dev->lna_gain;
1986 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
1997 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2045 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2059 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2081 for (i = 0; i < rt2x00dev->tx->limit; i++) {
2082 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4);
2091 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2116 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n",
2150 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2152 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
2154 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2157 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2166 spin_lock_irq(&rt2x00dev->irqmask_lock);
2168 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
2170 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2172 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2175 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2184 spin_lock_irq(&rt2x00dev->irqmask_lock);
2186 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR);
2188 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2190 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2195 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
2198 rt61pci_txdone(rt2x00dev);
2199 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2200 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2205 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
2206 rt2x00lib_beacondone(rt2x00dev);
2207 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2208 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2213 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
2215 if (rt2x00mmio_rxdone(rt2x00dev))
2216 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2217 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2218 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2223 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
2225 rt61pci_wakeup(rt2x00dev);
2226 rt2x00mmio_register_write(rt2x00dev,
2228 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2229 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2234 struct rt2x00_dev *rt2x00dev = dev_instance;
2242 reg_mcu = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR);
2243 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2245 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
2246 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2251 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2258 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2261 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2264 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2267 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2281 spin_lock(&rt2x00dev->irqmask_lock);
2283 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
2285 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2287 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR);
2289 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2291 spin_unlock(&rt2x00dev->irqmask_lock);
2299 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2307 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
2309 eeprom.data = rt2x00dev;
2319 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2325 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2326 rt2x00lib_set_mac_address(rt2x00dev, mac);
2328 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
2339 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2340 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
2343 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
2352 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2353 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
2356 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED);
2360 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2361 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
2364 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ);
2368 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2369 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
2372 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG);
2376 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2377 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2385 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2388 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A);
2392 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2393 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2401 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2407 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2416 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
2422 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0);
2423 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2426 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2427 !rt2x00_rf(rt2x00dev, RF5325) &&
2428 !rt2x00_rf(rt2x00dev, RF2527) &&
2429 !rt2x00_rf(rt2x00dev, RF2529)) {
2430 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
2438 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2443 rt2x00dev->default_ant.tx =
2445 rt2x00dev->default_ant.rx =
2452 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2458 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2463 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ);
2465 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2467 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2472 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
2475 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2477 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2484 if (rt2x00_rf(rt2x00dev, RF2529) &&
2485 !rt2x00_has_cap_double_antenna(rt2x00dev)) {
2486 rt2x00dev->default_ant.rx =
2488 rt2x00dev->default_ant.tx =
2492 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2494 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2503 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED);
2506 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2507 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2509 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2512 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2513 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2516 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2519 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2522 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2525 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2528 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2530 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2533 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2655 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2657 struct hw_mode_spec *spec = &rt2x00dev->spec;
2665 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2670 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
2671 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
2672 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
2673 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
2675 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2676 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2677 rt2x00_eeprom_addr(rt2x00dev,
2689 rt2x00dev->hw->max_rates = 1;
2690 rt2x00dev->hw->max_report_rates = 7;
2691 rt2x00dev->hw->max_rate_tries = 1;
2699 if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) {
2707 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2721 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2728 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2739 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2747 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2752 retval = rt61pci_validate_eeprom(rt2x00dev);
2756 retval = rt61pci_init_eeprom(rt2x00dev);
2764 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13);
2766 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
2771 retval = rt61pci_probe_hw_mode(rt2x00dev);
2779 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2784 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2785 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2787 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2788 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2793 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2806 struct rt2x00_dev *rt2x00dev = hw->priv;
2830 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2837 reg = rt2x00mmio_register_read(rt2x00dev, offset);
2839 rt2x00mmio_register_write(rt2x00dev, offset, reg);
2845 reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR);
2847 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg);
2849 reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR);
2851 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg);
2853 reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR);
2855 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg);
2862 struct rt2x00_dev *rt2x00dev = hw->priv;
2866 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13);
2868 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12);