intel/ipw2x00/ipw2200.c

387 #define ipw_read32(ipw, ofs) ({ \
548 	ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
554 	ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
711 		*((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
808 	priv->table0_len = ipw_read32(priv, priv->table0_addr);
813 	priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
819 	priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
1199 	return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1208 		base = ipw_read32(priv, IPW_EVENT_LOG);
1218 	u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1695 		reg = ipw_read32(priv, priv->direct_dword);
1716 	if (0 == (ipw_read32(priv, 0x30) & 0x10000)) {
1924 	inta = ipw_read32(priv, IPW_INTA_RW);
1925 	inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
2976 		if ((ipw_read32(priv, addr) & mask) == mask)
3562 	if (ipw_read32(priv, IPW_INTA_RW) & IPW_INTA_BIT_PARITY_ERROR) {
4967 	hw_tail = ipw_read32(priv, q->reg_r);
6090 	reg = ipw_read32(priv, IPW_MEM_FIXED_OVERRIDE);
8208 	r = ipw_read32(priv, IPW_RX_READ_INDEX);
8209 	ipw_read32(priv, IPW_RX_WRITE_INDEX);
10456 	inta = ipw_read32(priv, IPW_INTA_RW);
10457 	inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);