Lines Matching defs:data0
1262 u32 data0, data1, clock;
1268 data0 = data1 = 0;
1279 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1293 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1295 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1317 u32 data, data0, data1, data2;
1320 data = data0 = data1 = data2 = 0;
1326 * (3040/2). data0 is used to set the PLL divider and data1
1333 data0 = ((2 * (c - 704)) - 3040) / 10;
1339 data0 = ((2 * (c - 672)) - 3040) / 10;
1344 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1347 * and set using data2. LO is at 4800Hz and data0 is again used
1356 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1359 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1362 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1367 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1371 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1391 u32 data, data0, data2;
1394 data = data0 = data2 = 0;
1398 data0 = ath5k_hw_bitswap((c - 2272), 8);
1403 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1405 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1407 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1412 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1416 data = (data0 << 4) | data2 << 2 | 0x1001;