ath/ath11k/hal.c

273 	u32 reg_base;
275 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
278 		ath11k_hif_write32(ab, reg_base +
286 		ath11k_hif_write32(ab, reg_base +
290 				   reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET(ab),
294 	ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr);
301 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val);
305 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val);
316 			   reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab),
322 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab),
324 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab),
328 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2];
329 	ath11k_hif_write32(ab, reg_base, 0);
330 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET(ab), 0);
333 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
343 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val);
352 	u32 reg_base;
354 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
357 		ath11k_hif_write32(ab, reg_base +
365 		ath11k_hif_write32(ab, reg_base +
369 		ath11k_hif_write32(ab, reg_base +
374 	ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr);
381 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
384 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
387 		ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
393 		ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
408 			   reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab),
417 			   reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab),
425 				   reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab),
428 				   reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab),
433 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2];
434 	ath11k_hif_write32(ab, reg_base, 0);
435 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0);
438 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
452 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val);
968 	u32 reg_base;
1006 	reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2];
1023 				(u32 *)((unsigned long)ab->mem + reg_base);
1026 					   "type %d ring_num %d reg_base 0x%x shadow 0x%lx\n",
1028 					   reg_base,
1056 				(u32 *)((unsigned long)ab->mem + reg_base +
1062 					   reg_base + (HAL_REO1_RING_TP(ab) -