ath/ath11k/hal.c

193 static int ath11k_hal_alloc_cont_rdp(struct ath11k_base *ab)
195 	struct ath11k_hal *hal = &ab->hal;
199 	hal->rdp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->rdp.paddr,
207 static void ath11k_hal_free_cont_rdp(struct ath11k_base *ab)
209 	struct ath11k_hal *hal = &ab->hal;
216 	dma_free_coherent(ab->dev, size,
221 static int ath11k_hal_alloc_cont_wrp(struct ath11k_base *ab)
223 	struct ath11k_hal *hal = &ab->hal;
227 	hal->wrp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->wrp.paddr,
235 static void ath11k_hal_free_cont_wrp(struct ath11k_base *ab)
237 	struct ath11k_hal *hal = &ab->hal;
244 	dma_free_coherent(ab->dev, size,
249 static void ath11k_hal_ce_dst_setup(struct ath11k_base *ab,
252 	struct hal_srng_config *srng_config = &ab->hal.srng_config[HAL_CE_DST];
260 	val = ath11k_hif_read32(ab, addr);
264 	ath11k_hif_write32(ab, addr, val);
267 static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab,
270 	struct ath11k_hal *hal = &ab->hal;
278 		ath11k_hif_write32(ab, reg_base +
279 				   HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab),
286 		ath11k_hif_write32(ab, reg_base +
287 				       HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab), val);
289 		ath11k_hif_write32(ab,
290 				   reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET(ab),
294 	ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr);
301 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val);
305 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val);
315 	ath11k_hif_write32(ab,
316 			   reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab),
322 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab),
324 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab),
329 	ath11k_hif_write32(ab, reg_base, 0);
330 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET(ab), 0);
343 	ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val);
346 static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
349 	struct ath11k_hal *hal = &ab->hal;
357 		ath11k_hif_write32(ab, reg_base +
358 				   HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab),
365 		ath11k_hif_write32(ab, reg_base +
366 				       HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab),
369 		ath11k_hif_write32(ab, reg_base +
370 				       HAL_TCL1_RING_MSI1_DATA_OFFSET(ab),
374 	ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr);
381 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
384 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
387 		ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
393 		ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
407 	ath11k_hif_write32(ab,
408 			   reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab),
416 	ath11k_hif_write32(ab,
417 			   reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab),
424 		ath11k_hif_write32(ab,
425 				   reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab),
427 		ath11k_hif_write32(ab,
428 				   reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab),
434 	ath11k_hif_write32(ab, reg_base, 0);
435 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0);
452 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val);
455 static void ath11k_hal_srng_hw_init(struct ath11k_base *ab,
459 		ath11k_hal_srng_src_hw_init(ab, srng);
461 		ath11k_hal_srng_dst_hw_init(ab, srng);
464 static int ath11k_hal_srng_get_ring_id(struct ath11k_base *ab,
468 	struct hal_srng_config *srng_config = &ab->hal.srng_config[type];
472 		ath11k_warn(ab, "invalid ring number :%d\n", ring_num);
486 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type)
493 	srng_config = &ab->hal.srng_config[ring_type];
498 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type)
505 	srng_config = &ab->hal.srng_config[ring_type];
510 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng,
525 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab,
532 		return ab->hal.wrp.paddr +
534 			(unsigned long)ab->hal.wrp.vaddr);
536 		return ab->hal.rdp.paddr +
538 			 (unsigned long)ab->hal.rdp.vaddr);
541 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab,
548 		return ab->hal.rdp.paddr +
550 			(unsigned long)ab->hal.rdp.vaddr);
552 		return ab->hal.wrp.paddr +
554 			(unsigned long)ab->hal.wrp.vaddr);
619 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng)
629 static u32 *ath11k_hal_srng_dst_peek_with_dma(struct ath11k_base *ab,
643 static void ath11k_hal_srng_prefetch_desc(struct ath11k_base *ab,
650 	desc = ath11k_hal_srng_dst_peek_with_dma(ab, srng, &desc_paddr);
652 		dma_sync_single_for_cpu(ab->dev, desc_paddr,
659 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab,
679 		ath11k_hal_srng_prefetch_desc(ab, srng);
684 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng,
707 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng,
729 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab,
762 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab,
782 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab,
799 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng)
810 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, struct hal_srng *srng)
822 			ath11k_hal_srng_prefetch_desc(ab, srng);
829 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng)
850 			ath11k_hif_write32(ab,
852 					   (unsigned long)ab->mem,
856 			ath11k_hif_write32(ab,
858 					   (unsigned long)ab->mem,
866 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
890 	ath11k_hif_write32(ab,
894 	ath11k_hif_write32(ab,
898 	ath11k_hif_write32(ab,
903 	ath11k_hif_write32(ab,
914 	ath11k_hif_write32(ab,
919 	ath11k_hif_write32(ab,
928 	ath11k_hif_write32(ab,
934 	ath11k_hif_write32(ab,
939 	ath11k_hif_write32(ab,
947 	ath11k_hif_write32(ab,
953 	ath11k_hif_write32(ab,
955 			   HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab), 0x40);
958 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
962 	struct ath11k_hal *hal = &ab->hal;
963 	struct hal_srng_config *srng_config = &ab->hal.srng_config[type];
970 	ring_id = ath11k_hal_srng_get_ring_id(ab, type, ring_num, mac_id);
1021 			if (!ab->hw_params.supports_shadow_regs)
1023 				(u32 *)((unsigned long)ab->mem + reg_base);
1025 				ath11k_dbg(ab, ATH11K_DBG_HAL,
1030 					   (unsigned long)ab->mem);
1054 			if (!ab->hw_params.supports_shadow_regs)
1056 				(u32 *)((unsigned long)ab->mem + reg_base +
1057 					(HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab)));
1059 				ath11k_dbg(ab, ATH11K_DBG_HAL,
1062 					   reg_base + (HAL_REO1_RING_TP(ab) -
1063 						       HAL_REO1_RING_HP(ab)),
1065 					   (unsigned long)ab->mem);
1072 	ath11k_hal_srng_hw_init(ab, srng);
1076 		ath11k_hal_ce_dst_setup(ab, srng, ring_num);
1082 static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab,
1088 	struct ath11k_hal *hal = &ab->hal;
1092 	ring_id = ath11k_hal_srng_get_ring_id(ab, ring_type, ring_num, 0);
1099 		srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +
1100 						   (unsigned long)ab->mem);
1102 		srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +
1103 						   (unsigned long)ab->mem);
1106 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
1110 	struct ath11k_hal *hal = &ab->hal;
1131 	ath11k_hal_srng_update_hp_tp_addr(ab, shadow_cfg_idx, ring_type,
1134 	ath11k_dbg(ab, ATH11K_DBG_HAL,
1137 		  HAL_SHADOW_REG(ab, shadow_cfg_idx),
1144 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab)
1146 	struct ath11k_hal *hal = &ab->hal;
1162 			ath11k_hal_srng_update_shadow_config(ab, ring_type, ring_num);
1166 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab,
1169 	struct ath11k_hal *hal = &ab->hal;
1175 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab,
1185 		ath11k_hal_srng_access_end(ab, srng);
1188 static int ath11k_hal_srng_create_config(struct ath11k_base *ab)
1190 	struct ath11k_hal *hal = &ab->hal;
1200 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab);
1201 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP(ab);
1202 	s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab);
1203 	s->reg_size[1] = HAL_REO2_RING_HP(ab) - HAL_REO1_RING_HP(ab);
1206 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB(ab);
1207 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab);
1210 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
1211 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab);
1214 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
1215 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(ab);
1218 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
1219 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP(ab);
1222 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab);
1224 	s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab);
1228 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab);
1232 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab);
1236 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB +
1237 		ATH11K_CE_OFFSET(ab);
1238 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP +
1239 		ATH11K_CE_OFFSET(ab);
1240 	s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
1241 		HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
1242 	s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
1243 		HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
1246 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB +
1247 		ATH11K_CE_OFFSET(ab);
1248 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP +
1249 		ATH11K_CE_OFFSET(ab);
1250 	s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
1251 		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
1252 	s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
1253 		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
1256 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +
1257 		HAL_CE_DST_STATUS_RING_BASE_LSB + ATH11K_CE_OFFSET(ab);
1258 	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP +
1259 		ATH11K_CE_OFFSET(ab);
1260 	s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
1261 		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
1262 	s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
1263 		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
1266 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);
1270 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(ab);
1274 	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
1276 	s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) -
1277 		HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
1283 static void ath11k_hal_register_srng_key(struct ath11k_base *ab)
1285 	struct ath11k_hal *hal = &ab->hal;
1292 static void ath11k_hal_unregister_srng_key(struct ath11k_base *ab)
1294 	struct ath11k_hal *hal = &ab->hal;
1301 int ath11k_hal_srng_init(struct ath11k_base *ab)
1303 	struct ath11k_hal *hal = &ab->hal;
1308 	ret = ath11k_hal_srng_create_config(ab);
1312 	ret = ath11k_hal_alloc_cont_rdp(ab);
1316 	ret = ath11k_hal_alloc_cont_wrp(ab);
1320 	ath11k_hal_register_srng_key(ab);
1325 	ath11k_hal_free_cont_rdp(ab);
1332 void ath11k_hal_srng_deinit(struct ath11k_base *ab)
1334 	struct ath11k_hal *hal = &ab->hal;
1336 	ath11k_hal_unregister_srng_key(ab);
1337 	ath11k_hal_free_cont_rdp(ab);
1338 	ath11k_hal_free_cont_wrp(ab);
1343 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab)
1350 	ath11k_err(ab, "Last interrupt received for each CE:\n");
1351 	for (i = 0; i < ab->hw_params.ce_count; i++) {
1352 		ce_pipe = &ab->ce.ce_pipe[i];
1354 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
1357 		ath11k_err(ab, "CE_id %d pipe_num %d %ums before\n",
1362 	ath11k_err(ab, "\nLast interrupt received for each group:\n");
1364 		irq_grp = &ab->ext_irq_grp[i];
1365 		ath11k_err(ab, "group_id %d %ums before\n",
1371 		srng = &ab->hal.srng_list[i];
1377 			ath11k_err(ab,
1385 			ath11k_err(ab,