ath/ath10k/hw.h

389 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
392 int ath10k_hw_diag_fast_download(struct ath10k *ar,
397 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
398 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
399 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
400 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
401 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
402 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
403 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
404 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
405 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
644 	void (*set_coverage_class)(struct ath10k *ar, s16 value);
645 	int (*enable_pll_clk)(struct ath10k *ar);
773 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
839 #define CE_COUNT ar->hw_values->ce_count
853 #define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
856 #define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
866 #define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
867 #define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
871 #define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
876 #define WLAN_MAC_BASE_ADDRESS			ar->regs->wlan_mac_base_address
880 #define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
881 #define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
882 #define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
883 #define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
884 #define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
885 #define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
886 #define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
887 #define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
888 #define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
891 #define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
895 #define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
896 #define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
910 #define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
972 #define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
973 #define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
977 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
980 #define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
986 #define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
987 #define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all