ath/ath10k/hw.c

550 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
560 	wraparound_type = ar->hw_params.cc_wraparound_type;
585 	survey->time = CCNT_TO_MSEC(ar, cc);
586 	survey->time_busy = CCNT_TO_MSEC(ar, rcc);
592 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
605 	mutex_lock(&ar->conf_mutex);
608 	if ((ar->state != ATH10K_STATE_ON) &&
609 	    (ar->state != ATH10K_STATE_RESTARTED)) {
610 		spin_lock_bh(&ar->data_lock);
612 		ar->fw_coverage.coverage_class = value;
613 		spin_unlock_bh(&ar->data_lock);
620 	slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
622 	timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
624 	phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
629 		value = ar->fw_coverage.coverage_class;
634 	if (value == ar->fw_coverage.coverage_class &&
635 	    slottime_reg == ar->fw_coverage.reg_slottime_conf &&
636 	    timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
637 	    phyclk_reg == ar->fw_coverage.reg_phyclk)
641 	if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
642 		ar->fw_coverage.reg_slottime_orig = slottime_reg;
643 	if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
644 		ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
645 	ar->fw_coverage.reg_phyclk = phyclk_reg;
648 	slottime_reg = ar->fw_coverage.reg_slottime_orig;
649 	timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
653 		ath10k_warn(ar,
662 		ath10k_warn(ar,
693 	ath10k_hif_write32(ar,
696 	ath10k_hif_write32(ar,
705 	fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
706 	fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
714 	ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
718 	spin_lock_bh(&ar->data_lock);
719 	ar->fw_coverage.coverage_class = value;
720 	spin_unlock_bh(&ar->data_lock);
722 	ar->fw_coverage.reg_slottime_conf = slottime_reg;
723 	ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
726 	mutex_unlock(&ar->conf_mutex);
731  * @ar: the ath10k blob
741 static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar)
749 	hw = &ar->hw_params;
751 	if (ar->regs->core_clk_div_address == 0 ||
752 	    ar->regs->cpu_pll_init_address == 0 ||
753 	    ar->regs->cpu_speed_address == 0)
756 	clk_div_addr = ar->regs->core_clk_div_address;
757 	pll_init_addr = ar->regs->cpu_pll_init_address;
758 	speed_addr = ar->regs->cpu_speed_address;
762 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
774 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
781 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
787 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
793 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
799 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
805 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
811 	ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val,
818 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
825 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
833 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
850 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
856 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
864 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
881 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
887 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
893 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
898 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
904 	ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val,
910 	ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,
921 static void ath10k_hw_map_target_mem(struct ath10k *ar, u32 msb)
925 	ath10k_hif_write32(ar, address, msb);
936 static int ath10k_hw_diag_segment_msb_download(struct ath10k *ar,
945 	ath10k_hw_map_target_mem(ar, CPU_ADDR_MSB_REGION_VAL(address));
951 		ret = ath10k_hif_diag_write(ar, address, buffer, size);
953 			ath10k_warn(ar,
960 		ath10k_hw_map_target_mem(ar,
963 		ret = ath10k_hif_diag_write(ar,
967 			ath10k_warn(ar,
975 		ret = ath10k_hif_diag_write(ar, address, buffer, length);
977 			ath10k_warn(ar,
986 	ath10k_hw_map_target_mem(ar,
991 static int ath10k_hw_diag_segment_download(struct ath10k *ar,
998 		return ath10k_hw_diag_segment_msb_download(ar, buffer,
1001 		return ath10k_hif_diag_write(ar, address, buffer, length);
1004 int ath10k_hw_diag_fast_download(struct ath10k *ar,
1026 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1033 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1044 			ath10k_warn(ar, "firmware segment is truncated: %d\n",
1057 			ret = ath10k_bmi_set_start(ar, base_addr);
1068 			ath10k_warn(ar,
1076 				ath10k_warn(ar,
1083 			ret = ath10k_hw_diag_segment_download(ar,
1089 				ath10k_warn(ar,
1103 		ath10k_dbg(ar, ATH10K_DBG_BOOT,