ath/ath10k/hw.c

745 	u32 addr, reg_val, mem_val;
762 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
767 	if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)
770 	hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];
774 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
778 	reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);
779 	reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |
781 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
787 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
791 	reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;
792 	reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);
793 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
799 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
803 	reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;
804 	reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);
805 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
818 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
822 	reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |
825 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
833 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
837 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
845 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
850 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
854 	reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;
855 	reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);
856 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
864 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
868 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
876 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
881 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
885 	reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;
886 	reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);
887 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
893 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
897 	reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;
898 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);