Lines Matching refs:pef2256
10 #include <linux/framer/pef2256.h>
24 #include "pef2256-regs.h"
36 struct pef2256 {
54 static u8 pef2256_read8(struct pef2256 *pef2256, int offset)
58 regmap_read(pef2256->regmap, offset, &val);
62 static void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val)
64 regmap_write(pef2256->regmap, offset, val);
67 static void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr)
69 regmap_clear_bits(pef2256->regmap, offset, clr);
72 static void pef2256_setbits8(struct pef2256 *pef2256, int offset, u8 set)
74 regmap_set_bits(pef2256->regmap, offset, set);
77 static void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set)
79 regmap_update_bits(pef2256->regmap, offset, clr | set, set);
82 enum pef2256_version pef2256_get_version(struct pef2256 *pef2256)
87 vstr = pef2256_read8(pef2256, PEF2256_VSTR);
88 wid = pef2256_read8(pef2256, PEF2256_WID);
111 dev_err(pef2256->dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid);
158 static int pef2256_setup_gcm(struct pef2256 *pef2256)
165 mclk_rate = clk_get_rate(pef2256->mclk);
186 dev_err(pef2256->dev, "Unsupported v2.x MCLK rate %lu\n", mclk_rate);
192 if (pef2256->version == PEF2256_VERSION_1_2) {
201 pef2256_write8(pef2256, PEF2256_GCM(i + 1), *(gcm + i));
206 static int pef2256_setup_e1_line(struct pef2256 *pef2256)
211 pef2256_write8(pef2256, PEF2256_CMR1, 0x00);
218 pef2256_write8(pef2256, PEF2256_CMR2, PEF2256_CMR2_DCOXC);
220 if (pef2256->is_subordinate) {
222 pef2256_clrsetbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_RS_MASK,
229 if (pef2256->version == PEF2256_VERSION_1_2)
230 pef2256_write8(pef2256, PEF2256_LIM0, 0x00);
232 pef2256_write8(pef2256, PEF2256_LIM0, PEF2256_2X_LIM0_BIT3);
235 if (!pef2256->is_subordinate)
236 pef2256_setbits8(pef2256, PEF2256_LIM0, PEF2256_LIM0_MAS);
239 pef2256_write8(pef2256, PEF2256_LIM1, 0x00);
242 if (pef2256->version == PEF2256_VERSION_1_2)
243 pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_12_LIM1_RIL_MASK,
246 pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_2X_LIM1_RIL_MASK,
252 if (pef2256->version == PEF2256_VERSION_1_2)
253 pef2256_write8(pef2256, PEF2256_XPM0, 0x7B);
255 pef2256_write8(pef2256, PEF2256_XPM0, 0x9C);
256 pef2256_write8(pef2256, PEF2256_XPM1, 0x03);
257 pef2256_write8(pef2256, PEF2256_XPM2, 0x00);
260 pef2256_write8(pef2256, PEF2256_FMR0, PEF2256_FMR0_XC_HDB3 | PEF2256_FMR0_RC_HDB3);
268 switch (pef2256->frame_type) {
281 dev_err(pef2256->dev, "Unsupported frame type %d\n", pef2256->frame_type);
284 pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_XFS, fmr1);
285 pef2256_write8(pef2256, PEF2256_FMR2, fmr2);
287 if (!pef2256->is_subordinate) {
289 pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_SEC_IN_HIGH);
292 pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_FSC_OUT_HIGH);
298 pef2256_write8(pef2256, PEF2256_PC5, 0x00);
299 pef2256_write8(pef2256, PEF2256_PC6, 0x00);
302 pef2256_setbits8(pef2256, PEF2256_PC5, PEF2256_PC5_CRP);
307 static void pef2256_setup_e1_los(struct pef2256 *pef2256)
310 pef2256_write8(pef2256, PEF2256_PCD, 10);
312 pef2256_write8(pef2256, PEF2256_PCR, 21);
314 pef2256_write8(pef2256, PEF2256_LIM2, PEF2256_LIM2_SLT_THR50);
315 if (pef2256->is_subordinate) {
317 pef2256_setbits8(pef2256, PEF2256_LIM2, PEF2256_LIM2_ELT);
321 static int pef2256_setup_e1_system(struct pef2256 *pef2256)
330 pef2256_write8(pef2256, PEF2256_SIC1, 0x00);
331 pef2256_write8(pef2256, PEF2256_SIC2, 0x00);
332 pef2256_write8(pef2256, PEF2256_SIC3, 0x00);
334 if (pef2256->is_subordinate) {
336 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_XBS_MASK,
340 if (pef2256->version != PEF2256_VERSION_1_2) {
342 pef2256_setbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RTRI);
345 if (pef2256->is_tx_falling_edge) {
347 pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESX, PEF2256_SIC3_RESR);
350 pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESR, PEF2256_SIC3_RESX);
354 pef2256_write8(pef2256, PEF2256_XC0, 0);
355 pef2256_write8(pef2256, PEF2256_XC1, 4);
357 pef2256_write8(pef2256, PEF2256_RC0, 0);
358 pef2256_write8(pef2256, PEF2256_RC1, 4);
361 switch (pef2256->sysclk_rate) {
375 dev_err(pef2256->dev, "Unsupported sysclk rate %lu\n", pef2256->sysclk_rate);
378 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1);
381 switch (pef2256->data_rate) {
399 dev_err(pef2256->dev, "Unsupported data rate %u\n", pef2256->data_rate);
402 pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_SSD_MASK, fmr1);
403 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSD_MASK, sic1);
406 pef2256_clrsetbits8(pef2256, PEF2256_SIC2, PEF2256_SIC2_SICS_MASK,
407 PEF2256_SIC2_SICS(pef2256->channel_phase));
412 static void pef2256_setup_e1_signaling(struct pef2256 *pef2256)
415 pef2256_write8(pef2256, PEF2256_XSW, PEF2256_XSW_XY(0x1F));
418 pef2256_write8(pef2256, PEF2256_XSP, 0x00);
420 if (pef2256->is_subordinate) {
422 pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XTM);
426 pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XSIS);
427 pef2256_setbits8(pef2256, PEF2256_XSP, PEF2256_XSP_XSIF);
430 pef2256_write8(pef2256, PEF2256_TSWM, 0x00);
433 static void pef2256_setup_e1_errors(struct pef2256 *pef2256)
436 pef2256_setbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_ECM);
439 pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_ECMC);
442 pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_SWD);
445 pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_ASY4);
448 static int pef2256_setup_e1(struct pef2256 *pef2256)
453 ret = pef2256_setup_gcm(pef2256);
458 pef2256_write8(pef2256, PEF2256_FMR1, 0x00);
461 pef2256_write8(pef2256, PEF2256_GCR, 0x00);
464 ret = pef2256_setup_e1_line(pef2256);
469 pef2256_setup_e1_los(pef2256);
472 ret = pef2256_setup_e1_system(pef2256);
477 pef2256_setup_e1_signaling(pef2256);
480 pef2256_setup_e1_errors(pef2256);
483 pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_SCI);
486 pef2256_read8(pef2256, PEF2256_ISR2);
487 pef2256_clrbits8(pef2256, PEF2256_IMR2, PEF2256_INT2_LOS | PEF2256_INT2_AIS);
490 pef2256_write8(pef2256, PEF2256_CMDR, PEF2256_CMDR_RRES | PEF2256_CMDR_XRES);
494 static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
496 dev_warn_ratelimited(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
499 static bool pef2256_is_carrier_on(struct pef2256 *pef2256)
503 frs0 = pef2256_read8(pef2256, PEF2256_FRS0);
507 static void pef2256_isr2_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
512 carrier = pef2256_is_carrier_on(pef2256);
513 if (atomic_xchg(&pef2256->carrier, carrier) != carrier)
514 framer_notify_status_change(pef2256->framer);
520 static void (*pef2256_isr_handler[])(struct pef2256 *, u8, u8) = {
528 struct pef2256 *pef2256 = (struct pef2256 *)priv;
533 gis = pef2256_read8(pef2256, PEF2256_GIS);
537 isr = pef2256_read8(pef2256, PEF2256_ISR(n));
538 pef2256_isr_handler[n](pef2256, n, isr);
545 static int pef2256_check_rates(struct pef2256 *pef2256, unsigned long sysclk_rate,
557 dev_err(pef2256->dev, "Unsupported system clock rate %lu\n", sysclk_rate);
565 dev_err(pef2256->dev, "Unsupported data rate %lu with system clock rate %lu\n",
570 static int pef2556_of_parse(struct pef2256 *pef2256, struct device_node *np)
574 pef2256->data_rate = 2048000;
575 ret = of_property_read_u32(np, "lantiq,data-rate-bps", &pef2256->data_rate);
577 dev_err(pef2256->dev, "%pOF: failed to read lantiq,data-rate-bps\n", np);
581 ret = pef2256_check_rates(pef2256, pef2256->sysclk_rate, pef2256->data_rate);
585 pef2256->is_tx_falling_edge = of_property_read_bool(np, "lantiq,clock-falling-edge");
587 pef2256->channel_phase = 0;
588 ret = of_property_read_u8(np, "lantiq,channel-phase", &pef2256->channel_phase);
590 dev_err(pef2256->dev, "%pOF: failed to read lantiq,channel-phase\n",
594 if (pef2256->channel_phase >= pef2256->sysclk_rate / pef2256->data_rate) {
595 dev_err(pef2256->dev, "%pOF: Invalid lantiq,channel-phase %u\n",
596 np, pef2256->channel_phase);
610 { .name = "lantiq-pef2256-pinctrl", },
613 static int pef2256_add_audio_devices(struct pef2256 *pef2256)
615 const char *compatible = "lantiq,pef2256-codec";
622 for_each_available_child_of_node(pef2256->dev->of_node, np) {
640 ret = mfd_add_devices(pef2256->dev, 0, audio_devs, count, NULL, 0, NULL);
647 struct pef2256 *pef2256 = framer_get_drvdata(framer);
649 status->link_is_on = !!atomic_read(&pef2256->carrier);
655 struct pef2256 *pef2256 = framer_get_drvdata(framer);
658 dev_err(pef2256->dev, "Only E1 line is currently supported\n");
664 pef2256->is_subordinate = true;
667 pef2256->is_subordinate = false;
674 return pef2256_setup_e1(pef2256);
679 struct pef2256 *pef2256 = framer_get_drvdata(framer);
682 config->clock_type = pef2256->is_subordinate ? FRAMER_CLOCK_EXT : FRAMER_CLOCK_INT;
699 struct pef2256 *pef2256;
705 pef2256 = devm_kzalloc(&pdev->dev, sizeof(*pef2256), GFP_KERNEL);
706 if (!pef2256)
709 pef2256->dev = &pdev->dev;
710 atomic_set(&pef2256->carrier, 0);
712 pef2256->is_subordinate = true;
713 pef2256->frame_type = PEF2256_FRAME_E1_DOUBLEFRAME;
719 pef2256->regmap = devm_regmap_init_mmio(&pdev->dev, iomem,
721 if (IS_ERR(pef2256->regmap)) {
723 PTR_ERR(pef2256->regmap));
724 return PTR_ERR(pef2256->regmap);
727 pef2256->mclk = devm_clk_get_enabled(&pdev->dev, "mclk");
728 if (IS_ERR(pef2256->mclk))
729 return PTR_ERR(pef2256->mclk);
731 pef2256->sclkr = devm_clk_get_enabled(&pdev->dev, "sclkr");
732 if (IS_ERR(pef2256->sclkr))
733 return PTR_ERR(pef2256->sclkr);
735 pef2256->sclkx = devm_clk_get_enabled(&pdev->dev, "sclkx");
736 if (IS_ERR(pef2256->sclkx))
737 return PTR_ERR(pef2256->sclkx);
743 sclkr_rate = clk_get_rate(pef2256->sclkr);
744 sclkx_rate = clk_get_rate(pef2256->sclkx);
746 dev_err(pef2256->dev, "clk rate mismatch. sclkr %lu Hz, sclkx %lu Hz\n",
750 pef2256->sysclk_rate = sclkr_rate;
753 pef2256->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
754 if (IS_ERR(pef2256->reset_gpio))
755 return PTR_ERR(pef2256->reset_gpio);
756 if (pef2256->reset_gpio) {
757 gpiod_set_value_cansleep(pef2256->reset_gpio, 1);
759 gpiod_set_value_cansleep(pef2256->reset_gpio, 0);
763 pef2256->version = pef2256_get_version(pef2256);
764 switch (pef2256->version) {
777 dev_info(pef2256->dev, "Version %s detected\n", version_txt);
779 ret = pef2556_of_parse(pef2256, np);
784 pef2256->framer = devm_framer_create(pef2256->dev, NULL, &pef2256_framer_ops);
785 if (IS_ERR(pef2256->framer))
786 return PTR_ERR(pef2256->framer);
788 framer_set_drvdata(pef2256->framer, pef2256);
791 pef2256_write8(pef2256, PEF2256_IMR0, 0xff);
792 pef2256_write8(pef2256, PEF2256_IMR1, 0xff);
793 pef2256_write8(pef2256, PEF2256_IMR2, 0xff);
794 pef2256_write8(pef2256, PEF2256_IMR3, 0xff);
795 pef2256_write8(pef2256, PEF2256_IMR4, 0xff);
796 pef2256_write8(pef2256, PEF2256_IMR5, 0xff);
799 pef2256_read8(pef2256, PEF2256_ISR0);
800 pef2256_read8(pef2256, PEF2256_ISR1);
801 pef2256_read8(pef2256, PEF2256_ISR2);
802 pef2256_read8(pef2256, PEF2256_ISR3);
803 pef2256_read8(pef2256, PEF2256_ISR4);
804 pef2256_read8(pef2256, PEF2256_ISR5);
809 ret = devm_request_irq(pef2256->dev, irq, pef2256_irq_handler, 0, "pef2256", pef2256);
813 platform_set_drvdata(pdev, pef2256);
815 ret = mfd_add_devices(pef2256->dev, 0, pef2256_devs,
818 dev_err(pef2256->dev, "add devices failed (%d)\n", ret);
822 ret = pef2256_setup_e1(pef2256);
826 framer_provider = devm_framer_provider_of_register(pef2256->dev,
832 ret = pef2256_add_audio_devices(pef2256);
834 dev_err(pef2256->dev, "add audio devices failed (%d)\n", ret);
843 struct pef2256 *pef2256 = platform_get_drvdata(pdev);
846 pef2256_write8(pef2256, PEF2256_IMR0, 0xff);
847 pef2256_write8(pef2256, PEF2256_IMR1, 0xff);
848 pef2256_write8(pef2256, PEF2256_IMR2, 0xff);
849 pef2256_write8(pef2256, PEF2256_IMR3, 0xff);
850 pef2256_write8(pef2256, PEF2256_IMR4, 0xff);
851 pef2256_write8(pef2256, PEF2256_IMR5, 0xff);
855 { .compatible = "lantiq,pef2256" },
862 .name = "lantiq-pef2256",
870 struct regmap *pef2256_get_regmap(struct pef2256 *pef2256)
872 return pef2256->regmap;