net/phy/microchip_t1.c

111 	int rc = 0;
116 	rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);
117 	if (rc < 0)
121 	prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc);
130 		rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
136 	return rc;
143 	int rc = 0;
150 			rc = phy_write(phydev, offset, val);
152 			rc = phy_read(phydev, offset);
153 		return rc;
158 		rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);
159 		if (rc < 0)
160 			return rc;
169 		rc = lan937x_dsp_workaround(phydev, ereg, bank);
170 		if (rc < 0)
171 			return rc;
174 	rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
175 	if (rc < 0)
176 		return rc;
179 		rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA);
181 	return rc;
187 	int new = 0, rc = 0;
192 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);
193 	if (rc < 0)
194 		return rc;
196 	new = val | (rc & (mask ^ 0xFFFF));
197 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
199 	return rc;
213 	int rc;
218 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
220 	if (rc < 0)
221 		return rc;
225 		rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
226 		rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
229 		rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
230 		rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
233 		rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
234 		rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
237 		rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
238 		rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
245 			   PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc);
430 	int rc;
433 	rc = genphy_soft_reset(phydev);
434 	if (rc < 0)
435 		return rc;
438 	rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init));
439 	if (rc < 0)
440 		return rc;
442 	rc = genphy_read_master_slave(phydev);
443 	if (rc)
444 		return rc;
450 		rc = lan87xx_phy_init_cmd(phydev, slave_init,
452 		if (rc < 0)
453 			return rc;
456 	rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init));
457 	if (rc < 0)
458 		return rc;
465 	int rc, val = 0;
469 		rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
470 		if (rc < 0)
471 			return rc;
473 		rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
474 		if (rc < 0)
475 			return rc;
477 		rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
480 		if (rc < 0)
481 			return rc;
483 		rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
486 		if (rc < 0)
487 			return rc;
491 		rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
492 		if (rc < 0)
493 			return rc;
496 		rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
500 		rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
501 		if (rc < 0)
502 			return rc;
504 		rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
505 		if (rc < 0)
506 			return rc;
508 		rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
511 		if (rc < 0)
512 			return rc;
514 		rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
519 	return rc < 0 ? rc : 0;
550 	int rc = lan87xx_phy_init(phydev);
552 	return rc < 0 ? rc : 0;
615 	int rc, i;
617 	rc = microchip_cable_test_start_common(phydev);
618 	if (rc < 0)
619 		return rc;
623 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
625 	if (rc < 0)
626 		return rc;
629 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
631 	if (rc < 0)
632 		return rc;
634 	if ((rc & 0x4000) != 0x4000) {
636 		rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE,
638 		if (rc < 0)
639 			return rc;
640 		rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
642 		if (rc < 0)
643 			return rc;
646 		rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
648 		if (rc < 0)
649 			return rc;
654 			rc = access_ereg_modify_changed(phydev,
662 			rc = access_ereg(phydev, cable_test[i].mode,
667 		if (rc < 0)
668 			return rc;
757 	int rc = 0;
762 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
764 	if (rc < 0)
765 		return rc;
767 	if ((rc & 2) == 2) {
769 		rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
772 		if (rc < 0)
773 			return rc;
785 	int rc = 0;
787 	rc = phy_read(phydev, T1_MODE_STAT_REG);
788 	if (rc < 0)
789 		return rc;
791 	if (rc & T1_LINK_UP_MSK)
801 	rc = genphy_read_master_slave(phydev);
802 	if (rc < 0)
803 		return rc;
805 	rc = genphy_read_status_fixed(phydev);
806 	if (rc < 0)
807 		return rc;
809 	return rc;
841 	int rc;
843 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
845 	if (rc < 0)
846 		return rc;
848 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
850 	if (rc < 0)
851 		return rc;
853 	sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc);